參數(shù)資料
型號(hào)： CY7C1461AV33
廠商： Cypress Semiconductor Corp.
英文描述： 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM)
中文描述： 36兆位（1米x 36 / 2 M中的x 18/512K × 72）流體系結(jié)構(gòu)，通過(guò)與總線延遲（帶總線延遲結(jié)構(gòu)的的36 - Mbit通過(guò)的SRAM（100萬(wàn)x 36 / 2 M中的x 18/512K × 72）流的SRAM ）
文件頁(yè)數(shù)： 10/31頁(yè)
文件大?。?/td> 1141K
代理商： CY7C1461AV33
CY7C1461AV33
CY7C1463AV33
CY7C1465AV33
Document #: 38-05356 Rev. *F
Page 10 of 31
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQP
X
.
On the next clock rise the data presented to DQs and DQP
X
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW
X
signals. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33
provides byte write capability that is described in the truth
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select input selectively writes to only the desired
bytes. Bytes not selected during a byte write operation
remains unaltered. A synchronous self timed write mechanism
has been provided to simplify the write operations. Byte write
capability
has
been
included
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1461AV33/CY7C1463AV33/CY7C1465AV33
is a common IO device, data must not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQs and
DQP
X
inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs and DQP
X
are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
to
greatly
simplify
Burst Write Accesses
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Write opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW to load the initial address, as described in the
Single Write Access section above. When ADV/LD is driven
HIGH on the subsequent clock rise, the Chip Enables (CE
1
,
CE
2
, and CE
3
) and WE inputs are ignored and the burst
counter is incremented. The correct BW
X
inputs must be
driven in each cycle of the burst write, to write the correct bytes
of data.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3
, must remain inactive
for the duration of t
ZZREC
after the ZZ input returns LOW.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
I
DDZZ
Sleep mode standby current
ZZ > V
DD
– 0.2V
100
mA
t
ZZS
Device operation to ZZ
ZZ > V
DD
– 0.2V
2t
CYC
ns
t
ZZREC
ZZ recovery time
ZZ < 0.2V
2t
CYC
ns
t
ZZI
ZZ active to sleep current
This parameter is sampled
2t
CYC
ns
t
RZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
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CY7C1461AV33-117AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx36 3.3V NoBL FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1461AV33-133AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx36 3.3V NoBL FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1461AV33-133AXCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx36 3.3V NoBL FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1461AV33-133AXI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx36 3.3V NoBL FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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