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參數(shù)資料
| 型號： | CY7C1461AV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM) |
| 中文描述： | 36兆位（1米x 36 / 2 M中的x 18/512K × 72）流體系結(jié)構(gòu)，通過與總線延遲（帶總線延遲結(jié)構(gòu)的的36 - Mbit通過的SRAM（100萬x 36 / 2 M中的x 18/512K × 72）流的SRAM ） |
| 文件頁數(shù)： | 11/31頁 |
| 文件大?。?/td> | 1141K |
| 代理商： | CY7C1461AV33 |
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CY7C1461AV33
CY7C1463AV33
CY7C1465AV33
Document #: 38-05356 Rev. *F
Page 11 of 31
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
1
CE
2
CE
3
ZZ
ADV/LD WE
BW
X
OE
CEN
CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-State
Read Cycle (Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H
Data Out
(Q)
Read Cycle (Continue Burst)
Next
X
X
X
L
H
X
X
L
L
L->H
Data Out
(Q)
NOP/Dummy Read
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Dummy Read (Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
Write Cycle (Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Write Abort (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Ignore Clock Edge (Stall)
Current
X
X
X
L
X
X
X
X
H
L->H
–
Sleep Mode
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW
, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQP
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
X
= Tri-state when OE
is inactive or when the device is deselected, and DQs and DQP
X
= data when OE is active.
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| CY7C1461AV33-117AXC | 功能描述:靜態(tài)隨機存取存儲器 1Mx36 3.3V NoBL FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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