參數(shù)資料
型號(hào)： CY7C1461AV33
廠商： Cypress Semiconductor Corp.
英文描述： 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM)
中文描述： 36兆位（1米x 36 / 2 M中的x 18/512K × 72）流體系結(jié)構(gòu)，通過(guò)與總線延遲（帶總線延遲結(jié)構(gòu)的的36 - Mbit通過(guò)的SRAM（100萬(wàn)x 36 / 2 M中的x 18/512K × 72）流的SRAM ）
文件頁(yè)數(shù)： 8/31頁(yè)
文件大?。?/td> 1141K
代理商： CY7C1461AV33
CY7C1461AV33
CY7C1463AV33
CY7C1465AV33
Document #: 38-05356 Rev. *F
Page 8 of 31
Pin Definitions
Name
IO
Description
A
0
, A
1
, A
Input-
Synchronous
Address Inputs used to select one of the address locations
. Sampled at the rising edge of the
CLK. A
[1:0]
are fed to the two-bit burst counter.
Byte Write Inputs, Active LOW
. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
BW
A
, BW
B
BW
C
, BW
D
,
BW
E
, BW
F
,
BW
G
, BW
H
Input-
Synchronous
WE
Input-
Synchronous
Write Enable Input, Active LOW
. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load Input
. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD must be
driven LOW to load a new address.
CLK
Input-
Clock
Clock Input
. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE1
Input-
Synchronous
Chip Enable 1 Input, Active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device.
CE
2
Input-
Synchronous
Chip Enable 2 Input, Active HIGH
. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.
CE
3
Input-
Synchronous
Chip Enable 3 Input, Active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and
CE
2
to select/deselect the device.
OE
Input-
Asynchronous
Output Enable, asynchronous input, Active LOW
. Combined with the synchronous logic block
inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device is deselected.
CEN
Input-
Synchronous
Clock Enable Input, Active LOW
. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, use CEN to extend the previous cycle when required.
ZZ
Input-
Asynchronous
ZZ “Sleep” Input
. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQ
s
IO-
Synchronous
Bidirectional Data IO lines
. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ
s
and DQP
[A:D]
are placed in a tri-state condition.The outputs are automatically tri-stated during
the data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQP
X
IO-
Synchronous
Bidirectional Data Parity IO Lines.
Functionally, these signals are identical to DQ
s
.
During write
sequences, DQP
X
is controlled by BW
X
correspondingly.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to V
DD
or left floating selects interleaved
burst sequence.
V
DD
Power Supply
Power supply inputs to the core of the device
.
V
DDQ
IO Power
Supply
Power supply for the IO circuitry
.
V
SS
Ground
Ground for the device
.
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