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參數(shù)資料
| 型號： | CY7C43686AV-15AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | FIFO |
| 英文描述： | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| 中文描述： | 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 644K |
| 代理商： | CY7C43686AV-15AC |
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 34 of 40
Notes:
55. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, RENB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
56. If Port B size is word or byte, AEB is set LOW by the last word or byte Read from FIFO1, respectively.
57. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
, then AEB may transition HIGH one CLKB cycle later than shown.
58. FIFO2 Write (MBC = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
59. If Port C size is word or byte, t
is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
60. t
is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKC edge and rising CLKA edge is less than t
, then AEA may transition HIGH one CLKA cycle later than shown.
61. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 2 clock cycles for flag deassertion, but the flag will always be
asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to
“
Designing with
CY7C436xx Synchronous FIFOs
”
application note for more details on flag uncertainties.
Switching Waveforms
(continued)
CLKC
WENC
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[58, 59, 61]
X2 Word in FIFO2
t
ENH
t
ENS
t
SKEW2
[60]
(X2 + 2)Words in FIFO2
t
PAE
t
PAE
t
ENS
t
ENH
t
ENS
t
ENH
t
ENH
t
ENS
X2 Words in FIFO
(X2 + 1) Words in
FIFO2
(X2 + 2) Words in
FIFO2
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
t
ENH
t
ENS
t
PAF
[D
–
(Y1+1)] Words in FIFO1
(D
–
Y1) Words in FIFO1
CLKA
ENA
AFA
CLKB
RENB
[61, 62, 63, 64]
t
PAF
t
ENS
t
ENH
t
SKEW2
[65]
[D
–
(Y1 + 2)] Words in
FIFO1
t
ENS
t
ENH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43686AV-7AC | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7C43686AV-10AI | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7C43686AV-10AC | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7M194-10DC | x4 SRAM Module |
| CY7M194-12DC | x4 SRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43686AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP |
| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C441-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C441-30JC | 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC |
| CY7C441-30JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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