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參數(shù)資料
| 型號： | CY7C43686AV-15AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | FIFO |
| 英文描述： | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| 中文描述： | 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 35/40頁 |
| 文件大?。?/td> | 644K |
| 代理商： | CY7C43686AV-15AC |
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 35 of 40
Notes:
62. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
63. D = Maximum FIFO Depth =1K for the CY7C43646AV, 4K for the CY7C43666AV, and 16K for the CY7C43686AV.
64. If Port B size is word or byte, t
is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
65. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
, then AFA may transition HIGH one CLKB cycle later than shown.
66. If Port C size is word or byte, AFC is set LOW by the last word or byte Write, respectively.
67. t
is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the
rising CLKC edge and rising CLKA edge is less than t
SKEW2
, then AFC may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
ENH
t
ENS
t
PAF
[D
–
(Y2 + 1)] Words in FIFO2
(D
–
Y2) Words in
FIFO2
CLKC
WENC
AFC
CLKA
ENA
Timing for AFC when FIFO2 is Almost Full (CY Standard and FWFT Modes)
[58, 61, 63, 66]
t
ENS
t
ENH
t
PAF
[D
–
(Y2 + 2)] Words in
FIFO
t
SKEW2
[67]
t
ENS
t
ENH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43686AV-7AC | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7C43686AV-10AI | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7C43686AV-10AC | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7M194-10DC | x4 SRAM Module |
| CY7M194-12DC | x4 SRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43686AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP |
| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C441-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C441-30JC | 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC |
| CY7C441-30JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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