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參數資料
| 型號： | CY7C43686AV-7AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | FIFO |
| 英文描述： | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| 中文描述： | 16K X 36 BI-DIRECTIONAL FIFO, 6 ns, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128 |
| 文件頁數： | 22/40頁 |
| 文件大?。?/td> | 644K |
| 代理商： | CY7C43686AV-7AC |
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 22 of 40
Notes:
31. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in parallel when
FFA/IRA is HIGH.
32. t
is the minimum time between the rising CLKA edge and a rising CLKC for FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than t
, then FFC/IRC may transition HIGH one cycle later than shown.
33. It is not necessary to program offset register bits on consecutive clock cycles. Attempts to write into FIFO memory are ignored until FFA/IRA is set HIGH.
34. t
is the minimum time between the rising CLKA edge and a rising CLKC for FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than t
, then FFC/IRC may transition HIGH one cycle later than shown.
35. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Switching Waveforms
(continued)
t
FSS
Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
t
WFF
t
DS
t
FSS
t
FSH
t
FSH
t
ENS
t
ENH
t
DH
t
SKEW1
[32]
AFA Offset (Y1)
AFC Offset (Y2)
First Word to FIFO1
CLKA
MRS1, MRS2
SPM
FS1/SEN,
FS0/SD
FFA/IRA
ENA
A
0
35
CLKC
FFC/IRC
[31]
AEB Offset (X1)
AEA Offset (X2)
t
WFF
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
t
FSS
t
SPH
t
SENS
t
SEN
t
SEN
t
SENS
t
SDH
t
SDS
t
SDH
t
SD
t
SKEW1
[34]
t
WFF
AFA Offset (Y1) MSB
t
FSS
t
FSH
t
WFF
CLKA
MRS1, MRS2
SPM
FFA/IRA
FS1/SEN
CLKC
FFC/IRC
[33, 35]
FS0/SD
[35]
AEA Offset (X2) LSB
t
FSS
t
FSH
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C43686AV-10AI | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7C43686AV-10AC | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| CY7M194-10DC | x4 SRAM Module |
| CY7M194-12DC | x4 SRAM Module |
| CY7M199-20DMB | x8 SRAM Module |
相關代理商/技術參數 |
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| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C441-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C441-30JC | 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC |
| CY7C441-30JI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4421-10JXC | 功能描述:IC SYNC FIFO 64KX9 10NS 32PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數據速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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