參數(shù)資料
型號: CY7C43686AV-7AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: FIFO
英文描述: 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
中文描述: 16K X 36 BI-DIRECTIONAL FIFO, 6 ns, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128
文件頁數(shù): 32/40頁
文件大?。?/td> 644K
代理商: CY7C43686AV-7AC
CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 32 of 40
Notes:
51. If Port C size is word or byte, IRC is set LOW by the last word or byte Write of the long word, respectively.
52. t
is the minimum time between a rising CLKA edge and a rising CLKC edge for IRC to transition HIGH in the next CLKC cycle. If the time between the
rising CLKA edge and rising CLKC edge is less than t
SKEW1
, then the transition of IRC HIGH may occur one CLKC cycle later than shown.
Switching Waveforms
(continued)
Previous Word in FIFO2
Output Register
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
LOW
HIGH
FIFO2 Full
t
EN
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLK
t
CLK
t
CLK
t
SKEW1
[52]
t
DH
t
DS
t
ENH
t
ENS
Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A
0
35
CLKC
FFC/IRC
MBC
WENC
C
0
17
IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
[51]
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