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September 18, 2006
Document No. 001-05356 Rev. *B
2
CY8C20234, CY8C20334, CY8C20434 Final Data Sheet
PSoC Overview
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
CPU core, called the M8C, is a powerful processor with speeds
up to 12 MHz. The M8C is a two-MIPS, 8-bit Harvard architec-
ture microprocessor.
System Resources provide additional capability, such as a con-
figurable I2C slave/SPI master-slave communication interface
and various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.8V analog reference, which together support
capacitive sensing of up to 28 inputs.
The CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware per-
forms capacitive sensing and scanning without requiring exter-
nal components. Capacitive sensing is configurable on each
GPIO pin. Scanning of enabled CapSense pins can be com-
pleted quickly and easily across multiple ports.
Analog System Block Diagram
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins can
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive mea-
surement for applications such as touch sensing. Other
multiplexer applications include:
■
Complex capacitive sensing interfaces, such as sliders and
touchpads.
■
Chip-wide mux that allows analog input from any IO pin.
■
Crosspoint connection between any IO pin combinations.
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include low voltage detection and power on
reset. Brief statements describing the merits of each system
resource are presented below.
■
The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower for a
slower system clock).
■
Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.8V reference provides an absolute reference for
capacitive sensing.
■
The 5V maximum input, 3V fixed output, low-dropout regula-
tor (LDO) provides regulation for IOs. A register-controlled
bypass mode allows the user to disable the LDO.
IDAC
Reference
Buffer
Vr
Cinternal
A
Cap Sense Counters
Comparator
Mux
Mux
Refs
CapSense
Clock Select
Relaxation
Oscillator
(RO)
CSCLK
IMO