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Contents
CY8C22xxx Preliminary Data Sheet
10
Document No. 38-12009 Rev. *D
December 22, 2003
24.1.4
External Clock..............................................................................................254
Register Definitions............................................................................................................256
24.2.1
INT_CLR0 Register......................................................................................256
24.2.2
INT_MSK0 Register.....................................................................................256
24.2.3
OSC_CR0 Register......................................................................................256
24.2.4
OSC_CR1 Register......................................................................................257
24.2.5
OSC_CR2 Register......................................................................................257
24.2.6
OSC_CR3 Register......................................................................................258
24.2.7
OSC_CR4 Register......................................................................................258
24.2
25. Decimator
............................................................................................................259
25.1
Architectural Description....................................................................................................259
25.2
Register Definitions............................................................................................................259
25.2.1
DEC_DH Register........................................................................................259
25.2.2
DEC_DL Register ........................................................................................260
25.2.3
DEC_CR0 Register......................................................................................260
25.2.4
DEC_CR1 Register......................................................................................260
26. I2C
.......................................................................................................................261
26.1
Architectural Description....................................................................................................261
26.1.1
Basic I2C Data Transfer...............................................................................261
26.2
Application Description ......................................................................................................263
26.2.1
Slave Operation...........................................................................................263
26.2.2
Master Operation.........................................................................................264
26.3
Register Definitions............................................................................................................265
26.3.1
I2C_CFG Register .......................................................................................265
26.3.2
I2C_SCR Register .......................................................................................267
26.3.3
I2C_DR Register..........................................................................................269
26.3.4
I2C_MSCR Register ....................................................................................269
26.4
Timing Diagrams................................................................................................................270
26.4.1
Clock Generation.........................................................................................270
26.4.2
Enable and Command Synchronization.......................................................271
26.4.3
Basic Input/Output Timing............................................................................271
26.4.4
Status Timing ...............................................................................................272
26.4.5
Master Start Timing......................................................................................273
26.4.6
Master Restart Timing .................................................................................274
26.4.7
Master Stop Timing......................................................................................274
26.4.8
Master/Slave Stall Timing ............................................................................275
26.4.9
Master Lost Arbitration Timing.....................................................................275
26.4.10
Master Clock Synchronization .....................................................................276
27. POR and LVD
......................................................................................................277
27.1
Architectural Description....................................................................................................277
27.2
Register Definitions............................................................................................................277
27.2.1
VLT_CR Register.........................................................................................277
27.2.2
VLT_CMP Register......................................................................................277
28. Internal Voltage Reference
...................................................................................279
28.1
Architectural Description....................................................................................................279
28.2
Register Definitions............................................................................................................279
28.2.1
BDG_TR Register........................................................................................279