參數(shù)資料
型號: CY8CLED04DOCD1-56LTXI
廠商: Cypress Semiconductor Corp
文件頁數(shù): 15/55頁
文件大?。?/td> 0K
描述: IC POWERPSOC DEBUG 4CH 1A 56VQFN
特色產(chǎn)品: PowerPSoC? Embedded Power Controller
標(biāo)準(zhǔn)包裝: 260
系列: PowerPSoC® CY8CLED
核心處理器: M8C
芯體尺寸: 8-位
速度: 24MHz
連通性: DALI,DMX512,I²C,IrDA,SPI,UART/USART
外圍設(shè)備: LED,LVD,POR,PWM,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤
包裝: 托盤
產(chǎn)品目錄頁面: 698 (CN2011-ZH PDF)
配用: 428-2882-ND - KIT STARTER POWERPSOC LIGHTING
428-2281-ND - KIT EVAL POWERPSOC LIGHTING
428-2270-ND - KIT STARTER DEMO LIGHTING
其它名稱: 428-2923
CY8CLED04D01, CY8CLED04D02, CY8CLED04G01
CY8CLED03D01, CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *P
Page 22 of 55
12.4 CY8CLED03D0x 56-Pin Part Pinout (without OCD)
The CY8CLED03D01 and CY8CLED03D02 PowerPSoC devices are available with the following pinout information. Every port pin
(labeled with a “P” and “FN0”) is capable of Digital I/O.
Table 12-4. CY8CLED03D0x 56-Pin Part Pinout (QFN)
Pin
No.
Type
Name
Description
Figure 12-4. CY8CLED03D0x 56-Pin PowerPSoC Device
Digital
Rows
Analog
Columns
Power
Peripherals
1
I/O
I
P1[0]
GPIO/I2C SDA (Secondary)/
ISSP SDATA
2
I/O
I
P2[2]
GPIO/Direct Switch Cap connection
3
I/O
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
4
I/O
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1)/
Capsense Ref Cap
5
I/O
I
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
6
I/O
I
P1[1]
GPIO/I2C SCL (Secondary)/
ISSP SCLK
7
I/O
I
P1[5]
GPIO/I2C SDA (Primary)
8
I/O
I
P1[7]
GPIO/I2C SCL (Primary)
9
VSS
Digital Ground
10
NC
No Connect
11
NC
No Connect
12
NC
No Connect
13
NC
No Connect
14
I
XRES
External Reset
15
VDD
Digital Power Supply
16
VSS
Digital Ground
17
AVSS
Analog Ground
18
AVDD
Analog Power Supply
19
I
CSN2
Current Sense Negative Input -
CSA2
20
CSP2
Current Sense Positive Input and
Power Supply - CSA2
21
DNC[5]
Do Not Connect
22
DNC[5]
Do Not Connect
23
SREGCOMP Voltage Regulator Error Amp Comp
24
I
SREGFB
Regulator Voltage Mode Feedback
Node
25
I
SREGCSN
Current Mode Feedback Negative
26
I
SREGCSP
Current Mode Feedback Positive
27
O
SREGSW
Switch Mode Regulator OUT
28
SREGHVIN
Switch Mode Regulator IN
29
GDVDD
Gate Driver Power Supply
Pin
No.
Type
Name
Description
30
GDVSS
Gate Driver Ground
Digital
Rows
Analog
Columns
Power
Peripherals
31
PGND3[6]
Power FET Ground 3
44
GDVDD Gate Driver Power Supply
32
DNC[5]
Do Not Connect
45
I/O
FN0[0]
Function I/O
33
DNC[5]
Do Not Connect
46
I/O
FN0[1]
Function I/O
34
PGND2[6]
Power FET Ground 2
47
I/O
FN0[2]
Function I/O
35
O
GD2
External Low Side Gate Driver 2
48
I/O
FN0[3]
Function I/O
36
SW2
Power Switch 2
49
I
CSN0
Current Sense Negative Input 0
37
SW1
Power Switch 1
50
CSP0
Current Sense Positive Input and
Power Supply - CSA0
38
O
GD1
External Low Side Gate Driver 1
51
CSP1
Current Sense Positive Input and
Power Supply - CSA1
39
PGND1[6]
Power FET Ground 1
52
I
CSN1
Current Sense Negative Input 1
40
SW0
Power Switch 0
53
I/O
I
P0[4]
GPIO/Analog Input (Column 1) /
Bandgap Output
41
O
GD0
External Low Side Gate Driver 0
54
VDD
Digital Power Supply
42
PGND0[6]
Power FETGround 0
55
VSS
Digital Ground
43
GDVSS
Gate Driver Ground
56
I/O
I
P1[4]
GPIO / External Clock Input
Notes
5. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device.
6. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
NC
XRES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VD
D
VSS
AVS
S
AV
DD
CS
N2
C
SP2
DN
C
DN
C
SR
E
G
C
O
MP
SR
E
G
F
B
SR
E
G
C
S
N
SR
E
G
C
S
P
SR
E
G
H
V
IN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GD
VSS
GD
VDD
FN
0
[0]
FN
0
[1]
FN
0
[2]
FN
0
[3]
CSN
0
CSP
0
C
SP1
CS
N
1
P0
[4
]
VD
D
VS
S
P1
[4
]
43
44
45
46
47
48
49
50
51
52
53
54
55
56
PGND0
GD0
SW0
PGND1
GD1
SW1
SW2
GD2
PGND2
DNC
PGND3
GDVSS
GDVDD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
S
R
EG
SW
Exposed
Pad
QFN Top View
* Connect Exposed Pad to PGNDx
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