參數(shù)資料
型號(hào)： CY8CLED04DOCD1-56LTXI
廠商： Cypress Semiconductor Corp
文件頁(yè)數(shù)： 6/55頁(yè)
文件大?。?/td> 0K
描述： IC POWERPSOC DEBUG 4CH 1A 56VQFN
特色產(chǎn)品： PowerPSoC? Embedded Power Controller
標(biāo)準(zhǔn)包裝： 260
系列： PowerPSoC® CY8CLED
核心處理器： M8C
芯體尺寸： 8-位
速度： 24MHz
連通性： DALI，DMX512，I²C，IrDA，SPI，UART/USART
外圍設(shè)備： LED，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 14
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 698 (CN2011-ZH PDF)
配用： 428-2882-ND - KIT STARTER POWERPSOC LIGHTING
428-2281-ND - KIT EVAL POWERPSOC LIGHTING
428-2270-ND - KIT STARTER DEMO LIGHTING
其它名稱： 428-2923
CY8CLED04D01, CY8CLED04D02, CY8CLED04G01
CY8CLED03D01, CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *P
Page 14 of 55
Analog blocks are arranged in two columns of three blocks each,
which includes one continuous time (CT) and two switched
capacitor (SC) blocks, as shown in Figure 6-2. on page 14.
Figure 6-2. Analog System Block Diagram
6.3 Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin in ports 0 to 2.
Pins can be connected to the bus individually or in any
combination. The bus also connects to the analog system for
analysis with comparators and analog-to-digital converters. It
can be split into two sections for simultaneous dual-channel
processing. An additional analog input multiplexer provides a
second path to bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Track pad, finger sensing
■ Crosspoint connection between any I/O pin combinations
application notes AN2394 - CapSense Best Practices, AN2292
and AN47456 - Design Guide CapSense buttons with CSD.
Apart from these, there are a number of application notes on
Capacitive Sensing on the Cypress webbiest. The PowerPSoC
Technical Reference Manual provides details on the analog
system configuration that enables all I/Os in the device to be
CapSense inputs.
6.4 Additional System Resources
System resources provide additional capability useful in
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief
statements describing the merits of each resource follow.
■ Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
■ A decimator provides a custom hardware filter for digital signal
processing applications including creation of delta sigma
ADCs.
■ Low-voltage detection (LVD) interrupts signal the application of
falling voltage levels, while the advanced POR (power on reset)
circuit eliminates the need for a system supervisor.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. The designer can
generate additional clocks using digital PSoC blocks as clock
dividers.
■ The I
2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master applications are
supported.
■ An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■ Versatile analog multiplexer system.
ACol1Mux
Array
Array Input Configuration
Reference
Generators
Bandgap
Vdd
Vss
AGND=VBG
Microcontroller Interface (Address Bus, Data Bus, Etc.)
Interface to Digital
System
A
n
a
lo
g
M
u
x
Bu
s
Ri
g
h
t
ACM0
ACM1
AC1
P0[5]
P0[7]
P0[3]
P1[5]
P1[7]
P1[1]
P0[4]
P1[4]
P2[2]
ACol0Mux
ACI0[1:0]
ACI1[1:0]
An
al
o
g
M
u
x
Bu
s
L
e
ft
ACB00
ACB01
ASC10
ASD11
ASD20
ASC21
BCol1Mux
SplitMux Bit
P1[0]
AINX
CSA Buffered Output
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