參數(shù)資料
型號： CY8CLED04DOCD1-56LTXI
廠商： Cypress Semiconductor Corp
文件頁數(shù)： 4/55頁
文件大?。?/td> 0K
描述： IC POWERPSOC DEBUG 4CH 1A 56VQFN
特色產(chǎn)品： PowerPSoC? Embedded Power Controller
標(biāo)準(zhǔn)包裝： 260
系列： PowerPSoC® CY8CLED
核心處理器： M8C
芯體尺寸： 8-位
速度： 24MHz
連通性： DALI，DMX512，I²C，IrDA，SPI，UART/USART
外圍設(shè)備： LED，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 14
程序存儲器容量： 16KB（16K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤
包裝： 托盤
產(chǎn)品目錄頁面： 698 (CN2011-ZH PDF)
配用： 428-2882-ND - KIT STARTER POWERPSOC LIGHTING
428-2281-ND - KIT EVAL POWERPSOC LIGHTING
428-2270-ND - KIT STARTER DEMO LIGHTING
其它名稱： 428-2923
CY8CLED04D01, CY8CLED04D02, CY8CLED04G01
CY8CLED03D01, CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *P
Page 12 of 55
5.10 Digital Multiplexer
The PowerPSoC family’s digital MUX is a configurable switching
matrix that connects the power peripheral digital resources.
For a full matrix representation of all possible routing using this
MUX, refer to the PowerPSoC Technical Reference Manual.
This power peripheral digital multiplexer is independent of the
main PSoC digital buses or global interconnect of the PSoC core.
The digital multiplexer includes the following key features:
■ Connect signals to ensure needed flexibility
5.11 Function Pins (FN0[0:3])
The function I/O pins are a set of dedicated control pins used to
perform system level functions with the power peripheral blocks
of the PowerPSoC. These pins are dynamically configurable,
enabling them to perform a multitude of input and output
functions. These I/Os have direct access to the input and output
of the voltage comparators, input of the hysteretic controller, and
output of the digital PWM blocks for the device. The function I/O
pins are register mapped. The microcontroller can control and
read the state of these pins and the interrupt function.
Some of the key system benefits of the function I/O are:
■ Enabling an external higher voltage current-sense amplifier as
shown in Figure 5-5.
■ Synchronizing dimming of multiple PowerPSoC controllers as
shown in Figure 5-6.
■ Programmable fail-safe monitor and dedicated shutdown of
hysteretic controller as shown in Figure 5-7.
Along with the these functions, these I/Os also provide interrupt
functionality, enabling intelligent system responses to power
control lighting system status.
Figure 5-5. External CSA and FET Application
Figure 5-6. PowerPSoC in Master/Slave Configuration
Figure 5-7. Event Detection
FN0[0]
FN0[3]
FN0[2]
FN0[1]
Hysteretic Mode
Controller 0
External
Gate Drive 0
DAC0
DAC1
HVDD
GD 0
.
VLED > 32V
External CSA
Rsense
+
-
External FET
{
.
PowerPSoC
Hysteretic Mode
Controller 3
External
Gate Drive 3
DAC6
DAC7
GD 3
PowerPSoC
(Master)
FN0[0]
FN0[2]
FN0[1]
FN0[3]
FN0[x]
PowerPSoC
(Slave 1)
Hysteretic
Controller
DIM
PowerPSoC
(Slave 3)
Hysteretic
Controller
DIM
PowerPSoC
(Slave 2)
Hysteretic
Controller
DIM
PowerPSoC
(Slave 0)
Hysteretic
Controller
DIM
FN0[x]
FN0[0]
Hysteretic Mode
Controller 0
External
Gate Drive 0
.
Event Detect
Trip
FN0[3]
Hysteretic Mode
Controller 3
Event Detect
Trip
.
External
Gate Drive 3
GD0
GD3
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