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參數(shù)資料
| 型號： | CYV15G0201DXB-BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Dual-channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, 1.50 MM HEIGHT, FBGA-196 |
| 文件頁數(shù)： | 15/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CYV15G0201DXB-BBC |
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CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 15 of 46
At the end of this sequence, if the TXCTx[1:0] = 11 condition
is sampled again, the sequence restarts and remains uninter-
ruptible for the following 15 character clocks.
If parity checking is enabled, the character used to start the
Word Sync Sequence must also have correct ODD parity.
Once the sequence is started, parity is not checked on the
following 15 characters in the Word Sync Sequence.
When TXMODE[1] = HIGH (TX modes 6, 7, and 8), the gener-
ation of the Word Sync Sequence becomes an interruptible
operation. In TX Mode 6, this sequence is started as soon as
the TXCTx[1:0] = 11 condition is detected on a channel. In
order for the sequence to continue on that channel, the
TXCTx[1:0] inputs must be sampled as 00 for the remaining
15 characters of the sequence.
If at any time a sample period exists where TXCTx[1:0]
≠
00,
the Word Sync Sequence is terminated, and a character repre-
senting the associated data and control bits is generated by
the Encoder. This resets the Word Sync Sequence state
machine such that it will start at the beginning of the sequence
at the next occurrence of TXCTx[1:0] = 11.
When parity checking is enabled and TXMODE[1] = HIGH, all
characters (including those in the middle of a Word Sync
Sequence) must have correct parity. The detection of a
character with incorrect parity during a Word Sync Sequence
(regardless of the state of TXCTx[1:0]) will interrupt that
sequence and force generation of a C0.7 SVS character. Any
interruption of the Word Sync Sequence causes the sequence
to terminate.
When TXCKSEL = LOW, the Input Registers for both transmit
channels are clocked by REFCLK
[4]
. When TXCKSEL =
HIGH, the Input Registers for both transmit channels are
clocked with TXCLKA
↑
. In these clock modes both sets of
TXCTx[1:0] inputs operate synchronous to the SCSEL
input.
[11]
TX Mode 4—Atomic Word Sync and SCSEL Control of
Word Sync Sequence Generation
When configured in TX Mode 4, the SCSEL input is captured
along with the associated TXCTx[1:0] data control inputs.
These bits combine to control the interpretation of the
TXDx[7:0] bits and the characters generated by them. These
bits are interpreted as listed in
Table 6
.
When TXCKSEL = MID, both transmit channels operate
independently. The SCSEL input is sampled only by
TXCLKA
↑
. When the character accepted in the Channel-A
Input Register has passed any selected validation and is ready
to be passed to the Encoder, the level captured on SCSEL is
passed to the Encoder of Channel-B during this same cycle.
Changing the state of SCSEL changes the relationship of the
characters on the alternate channel. SCSEL should either be
used as a static configuration input or changed only when the
state of TXCTx[1:0] on the alternate channel are such that
SCSEL is ignored during the change.
TX Mode 4 also supports an Atomic Word Sync Sequence.
Unlike TX Mode 3, this sequence is started when both SCSEL
and TXCTx[0] are sampled HIGH. With the exception of the
combination of control bits used to initiate the sequence, the
generation and operation of this Word Sync Sequence is the
same as that documented for TX Mode 3.
TX Mode 5—Atomic Word Sync, No SCSEL
When configured in TX Mode 5, the SCSEL signal is not used.
In addition to the standard character encodings, both with and
without atomic Word Sync Sequence generation, two
additional encoding mappings are controlled by the Channel
Bonding selection made through the RXMODE[1:0] inputs.
For non-bonded operation, the TXCTx[1:0] inputs for each
channel control the characters generated by that channel. The
specific characters generated by these bits are listed in
Table 7
.
TX Mode 5 also has the capability of generating an atomic
Word Sync Sequence. For the sequence to be started, the
TXCTx[1:0] inputs must both be sampled HIGH. With the
exception of the combination of control bits used to initiate the
sequence, the generation and operation of this Word Sync
Sequence is the same as that documented for TX Mode 3.
Two additional encoding maps are provided for use when
receive channel bonding is enabled. When dual-channel
bonding
is
enabled
CYP(V)15G0201DXB is configured such that channels A and
B are bonded together to form a two-character-wide path.
When operated in this two-channel bonded mode, the
TXCTA[0] and TXCTB[0] inputs control the interpretation of the
data on both the A and B channels. The characters on each
half of these bonded channels are controlled by the associated
TXCTx[1] bit. The specific characters generated by these
control bit combinations are listed in
Table 8
.
(RXMODE[1] = HIGH),
the
Note:
11.
When operated in any configuration where receive channels are bonded together, TXCKSEL must be either LOW or HIGH (not MID) to ensure that associated
characters are transmitted in the same character cycle.
Table 6. TX Modes 4 and 7 Encoding
S
T
T
Characters Generated
X
X
0
Encoded data character
0
0
1
K28.5 fill character
0
1
1
Special character code
1
X
1
16-character Word Sync Sequence
Table 7. TX Modes 5 and 8 Encoding, Non-Bonded
(RXMODE[1] = LOW)
S
T
T
Characters Generated
X
0
0
Encoded data character
X
0
1
K28.5 fill character
X
1
0
Special character code
X
1
1
16-character Word Sync Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CYV15G0201DXB-BBI | 制造商:Cypress Semiconductor 功能描述: |
| CYV15G0201DXB-BBXC | 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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| CYV15G0203TB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Serializer |
| CYV15G0203TB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Serializer |
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