參數(shù)資料
型號(hào)： CYV15G0201DXB-BBC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Dual-channel HOTLink II Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA196
封裝： 15 X 15 MM, 1.50 MM HEIGHT, FBGA-196
文件頁數(shù)： 9/46頁
文件大小： 577K
代理商： CYV15G0201DXB-BBC
CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 9 of 46
DECMODE
3-Level Select
[5]
Static Control Input
Decoder Mode Select
.
This input selects the behavior of the Decoder block.
When LOW, the Decoder is bypassed and raw 10-bit characters are passed to the Output
Register. When the Decoder is bypassed, RXCKSEL must be MID.
When MID, the Decoder is enabled and the Cypress Decoder table for Special Code
characters is used. When HIGH, the Decoder is enabled and the alternate Decoder table
for Special Code characters is used. See
Table 25
for a list of the Special Codes supported
in both encoded modes.
Receive Operating Mode
.
These inputs are interpreted to select one of nine operating
modes of the receive path. See
Table 13
for details.
Reframe Enable for All Channels
. Active HIGH. When HIGH, the framers in both channels
are enabled to frame per the presently enabled framing mode and selected framing
character.
Reframe Mode Select
. Used to control the type of character framing used to adjust the
character boundaries (based on detection of one or more framing characters in the received
serial bit stream). This signal operates in conjunction with the presently enabled channel
bonding mode, and the type of framing character selected.
When LOW, the low-latency framer is selected. This will frame on each occurrence of the
selected framing character(s) in the received data stream. This mode of framing stretches
the recovered clock for one or multiple cycles to align that clock with the recovered data.
When MID, the Cypress-mode multi-byte parallel framer is selected. This requires a pair of
the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits,
before the character boundaries are adjusted. The recovered character clock remains in the
same phasing regardless of character offset.
When HIGH, the alternate mode multi-byte parallel framer is selected. This requires
detection of the selected framing character(s) of the allowed disparities in the received serial
bit stream, on identical 10-bit boundaries, on four directly adjacent characters. The
recovered character clock remains in the same phasing regardless of character offset.
Framing Character Select
. Used to control the character or portion of a character used for
character framing of the received data streams.
When MID, the framer looks for both positive and negative disparity versions of the 8-bit
Comma character. When HIGH, the framer looks for both positive and negative disparity
versions of the K28.5 character. Configuring FRAMCHAR to LOW is reserved for
component test.
RXMODE[1:
0]
RFEN
3-Level Select
[5]
Static Control Inputs
LVTTL input,
asynchronous,
internal pull-down
3-Level Select
[5]
Static Control Input
RFMODE
FRAMCHAR 3-Level Select
[5]
Static Control Input
Device Control Signals
PARCTL
3-Level Select
[5]
Static Control Input
Parity Check/Generate Control
. Used to control the different parity check and generate
functions.
When LOW, parity checking is disabled, and the RXOPx outputs are all disabled (High-Z).
When
MID,
and
the
Encoder/Decoder
DECMODE
≠
LOW), TXDx[7:0] inputs are checked (along with TXOPx) for valid ODD parity,
and ODD parity is generated for the RXDx[7:0] outputs and presented on RXOPx. When
the Encoder and Decoder are disabled (TXMODE[1]
=
LOW, DECMODE
=
LOW), the
TXDx[7:0] and TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity, and
ODD parity is generated for the RXDx[7:0] and RXSTx[1:0] outputs and presented on
RXOPx. When HIGH, parity checking and generation are enabled. The TXDx[7:0] and
TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is
generated for the RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx.
are
enabled
(TXMODE[1]
≠
LOW,
Pin Descriptions
CYP(V)15G0201DXB Dual HOTLink II Transceiver (continued)
Pin Name
I/O Characteristics
Signal Description
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