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| 型號(hào)： | CYV15G0201DXB-BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Dual-channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, 1.50 MM HEIGHT, FBGA-196 |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CYV15G0201DXB-BBC |
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CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 19 of 46
Framing Character
The CYP(V)15G0201DXB allows selection of two combina-
tions of framing characters to support requirements of different
interfaces. The selection of the framing character is made
through the FRAMCHAR input.
The specific bit combinations of these framing characters are
listed in
Table 12
. When the specific bit combination of the
selected framing character is detected by the framer, the
boundaries of the characters present in the received data
stream are known.
Framer
The framer on each channel operates in one of three different
modes, as selected by the RFMODE input. In addition, the
framer itself may be enabled or disabled through the RFEN
input. When RFEN = LOW, the framers in both receive paths
are disabled, and no combination of bits in a received data
stream
will
alter
the
character
RFEN = HIGH, the framer selected by RFMODE is enabled on
both channels.
When RFMODE = LOW, the low-latency framer is selected.
This framer operates by stretching the recovered character
clock until it aligns with the received character boundaries. In
this mode the framer starts its alignment process on the first
detection of the selected framing character. To reduce the
impact on external circuits that make use of a recovered clock,
the clock period is not stretched by more than two bit-periods
in any one clock cycle. When operated in with a character-rate
output clock (RXRATE = LOW), the output of properly framed
characters may be delayed by up to nine character-clock
cycles from the detection of the selected framing character.
When operated with a half-character-rate output clock
(RXRATE = HIGH), the output of properly framed characters
may be delayed by up to 14 character-clock cycles from the
detection of the selected framing character.
[16]
When RFMODE is MID (open) the Cypress-mode multi-byte
framer is selected. The required detection of multiple framing
characters makes the associated link much more robust to
incorrect framing due to aliased SYNC characters in the data
stream. In this mode, the framer does not adjust the character
clock boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered
clock will not contain any significant phase changes or hops
during normal operation or framing, and allows the recovered
clock to be replicated and distributed to other external circuits
or components using PLL-based clock distribution elements.
In this framing mode the character boundaries are only
adjusted if the selected framing character is detected at least
Notes:
15. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the 8th bit
as an inversion of the 7th bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
16. When Receive BIST is enabled on a channel, the Low-latency Framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character,
which causes the Receiver to update its character boundaries incorrectly.
boundaries.
When
twice within a span of 50 bits, with both instances on identical
10-bit character boundaries.
When RFMODE = HIGH, the alternate-mode multi-byte
framer is enabled. Like the Cypress-mode multi-byte framer,
multiple framing characters must be detected before the
character boundary is adjusted. In this mode, the data stream
must contain a minimum of four of the selected framing
characters, received as consecutive characters, on identical
10-bit boundaries, before character framing is adjusted. In this
mode, the Framer does not adjust the character clock
boundary, but instead aligns the character to the already
recovered character clock.
Framing for all channels is enabled when RFEN = HIGH. If
RFEN = LOW, the framer for each channel is disabled. When
the framers are disabled, no changes are made to the
recovered character boundaries on any channel, regardless of
the presence of framing characters in the data stream.
10B/8B Decoder Block
The Decoder logic block performs three primary functions:
decoding the received transmission characters back into
Data and Special Character codes,
comparing generated BIST patterns with received
generation of ODD parity on the decoded characters.
10B/8B Decoder
The framed parallel output of each deserializer shifter is
passed to the 10B/8B Decoder where, if the Decoder is
enabled (DECMODE
≠
LOW), it is transformed from a 10-bit
transmission character back to the original Data and Special
Character codes. This block uses the 10B/8B Decoder
patterns in
Table 24
and
Table 25
of this data sheet. Valid data
characters are indicated by a 000b bit-combination on the
associated RXSTx[2:0] status bits, and Special Character
codes are indicated by a 001b bit-combination on these same
status outputs. Framing characters, invalid patterns, disparity
errors, and synchronization status are presented as alternate
combinations of these status bits.
The 10B/8B Decoder operates in two normal modes, and can
also be bypassed. The operating mode for the Decoder is
controlled by the DECMODE input.
When DECMODE = LOW, the Decoder is bypassed and raw
10-bit characters are passed to the Output Register. In this
mode, channel bonding is not possible, the receive Elasticity
Buffers are bypassed, and RXCKSEL must be MID. This clock
mode generates separate RXCLKx±
outputs for each receive
channel.
When DECMODE = MID (or open), the 10-bit transmission
characters are decoded using
Table 24
and
Table 25
.
Received Special Code characters are decoded using the
Cypress column of
Table 25
.
When DECMODE = HIGH, the 10-bit transmission characters
are decoded using
Table 24
and
Table 25
. Received Special
Code characters are decoded using the Alternate column of
Table 25
.
Table 12. Framing Character Selector
FRAMCHAR
LOW
MID (Open)
Bits Detected in Framer
Character Name
Reserved for test
Comma+
Comma–
–K28.5
+K28.5
Bits Detected
00111110XX
[15]
or 11000001XX
0011111010 or
1100000101
HIGH
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CYV15G0201DXB-BBI | 制造商:Cypress Semiconductor 功能描述: |
| CYV15G0201DXB-BBXC | 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0201DXB-BBXI | 功能描述:電信線路管理 IC Dual Ch Video IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0203TB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Serializer |
| CYV15G0203TB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Serializer |
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