- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378517 > CYV15G0201DXB (Cypress Semiconductor Corp.) Dual-channel HOTLink II Transceiver PDF資料下載
參數(shù)資料
| 型號： | CYV15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual-channel HOTLink II Transceiver |
| 中文描述： | 雙通道HOTLink II收發(fā)器 |
| 文件頁數(shù)： | 11/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CYV15G0201DXB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 11 of 46
OELE
LVTTL Input,
asynchronous,
internal pull-up
Serial Driver Output Enable Latch Enable
.
Active HIGH. When OELE = HIGH, the signals
on the BOE[3:0] inputs directly control the OUTxy
±
differential drivers. When the BOE[x]
input is HIGH, the associated OUTxy
±
differential driver is enabled. When the BOE[x] input
is LOW, the associated OUTxy
±
differential driver is powered down. When OELE returns
LOW, the last values present on BOE[3:0] are captured in the internal Output Enable Latch.
The specific mapping of BOE[3:0] signals to transmit output enables is listed in
Table 9
.
If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable all outputs.
Receive Channel Power-Control Latch Enable
. Active HIGH. When RXLE = HIGH, the
signals on the BOE[3:0] inputs directly control the power enables for the receive PLLs and
analog logic. When the BOE[3:0] input is HIGH, the associated receive channel A and
receive channel B PLL and analog logic are active. When the BOE[3:0] input is LOW, the
associated receive channel A and receive channel B PLL and analog logic are placed in a
non-functional power saving mode. When RXLE returns LOW, the last values present on
BOE[3:0] are captured in the internal RX PLL Enable Latch. The specific mapping of
BOE[3:0] signals to the associated receive channel enables is listed in
Table 9
. When the
device is reset (TRSTZ is sampled LOW), the latch is reset to disable both receive channels.
Transmit and Receive BIST Latch Enable
. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[3:0] inputs directly control the transmit and receive BIST enables. When
the BOE[x] input is LOW, the associated transmit or receive channel is configured to
generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associated
transmit or receive channel is configured for normal data transmission or reception. When
BISTLE returns LOW, the last values present on BOE[3:0] are captured in the internal BIST
Enable Latch. The specific mapping of BOE[3:0] signals to transmit and receive BIST
enables is listed in
Table 9
. When the latch is closed, if the device is reset (TRSTZ is sampled
LOW), the latch is reset to disable BIST on all transmit and receive channels.
BIST, Serial Output, and Receive Channel Enables
. These inputs are passed to and
through the Output Enable Latch when OELE = HIGH, and captured in this latch when
OELE returns LOW. These inputs are passed to and through the BIST Enable Latch when
BISTLE = HIGH, and captured in this latch when BISTLE returns LOW. These inputs are
passed to and through the Receive Channel Enable Latch when RXLE = HIGH, and
captured in this latch when RXLE returns LOW.
Link Fault Indication Output
. Active LOW. LFIx is the logical OR of four internal conditions:
1. Received serial data frequency outside expected range.
2. Analog amplitude below expected levels.
3. Transition density lower than expected.
4. Receive Channel disabled.
RXLE
LVTTL Input,
asynchronous,
internal pull-up
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
BOE[3:0]
LVTTL Input,
asynchronous,
internal pull-up
LFIA
LFIB
LVTTL Output,
Asynchronous
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select
. Used to control access to the JTAG Test Modes. If maintained HIGH for
>5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset automat-
ically upon application of power to the device.
JTAG Test Clock
.
TCLK
LVTTL Input,
internal pull-down
3-State
LVTTL Output
LVTTL Input,
internal pull-up
TDO
Test Data Out
. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
Test Data In
. JTAG data input port.
TDI
Power
V
CC
GND
+3.3V power.
Signal and Power Ground for all internal circuits.
Pin Descriptions
CYP(V)15G0201DXB Dual HOTLink II Transceiver (continued)
Pin Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0201DXB-BBC | Dual-channel HOTLink II Transceiver |
| CYV15G0404RB-BGC | Independent Clock Quad HOTLink Reclocking Deserializer |
| CYW15G0101DXB | Single-channel HOTLink II Transceiver(單通道熱連接II收發(fā)器) |
| CYW2315 | Serial Input PLL with 1.2-GHz Prescaler(帶1.2-GHz 預標定器的串聯(lián)輸入PLL) |
| CYW2320 | Serial Input PLL with 2.0-GHz Prescaler(帶2.0-GHz 預標定器的串聯(lián)輸入PLL) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0201DXB-BBI | 制造商:Cypress Semiconductor 功能描述: |
| CYV15G0201DXB-BBXC | 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0201DXB-BBXI | 功能描述:電信線路管理 IC Dual Ch Video IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0203TB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Serializer |
發(fā)布緊急采購，3分鐘左右您將得到回復。