- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378517 > CYV15G0201DXB (Cypress Semiconductor Corp.) Dual-channel HOTLink II Transceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | CYV15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual-channel HOTLink II Transceiver |
| 中文描述： | 雙通道HOTLink II收發(fā)器 |
| 文件頁數(shù)： | 21/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CYV15G0201DXB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 21 of 46
RXCLKA± and RXCLKC+ outputs presents buffered and
delayed forms of REFCLK. In this mode, the receive Elasticity
Buffers are enabled. For REFCLK clocking, the Elasticity
Buffers must be able to insert K28.5 characters and delete
framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel, however, the actual timing
on these insertions and deletions is controlled in part by the
how the transmitter sends its data. Insertion of a K28.5
character can only occur when the receiver has a framing
character in the Elasticity Buffer. Likewise, to delete a framing
character, one must also be in the Elasticity Buffer. To prevent
a receive buffer overflow or underflow on a receive channel, a
minimum density of framing characters must be present in the
received data streams.
When RXCKSEL = MID (or open), each received channel
Output Register is clocked by the recovered clock for that
channel. Since no characters may be added or deleted, the
receiver Elasticity Buffer is bypassed.
When RXCKSEL = HIGH, all channels are clocked by the
selected recovered clock. This selected clock is always output
on RXCLKA±. In this mode the receive Elasticity Buffers are
enabled. When data is output using a recovered clock
(RXCKSEL = HIGH), receive channels are not allowed to
insert and delete characters, except as necessary for Elasticity
Buffer alignment.
When the Elasticity Buffer is used, prior to delivery of valid data,
a Word Sync Sequence (or at least four framing characters)
must be received to center the Elasticity Buffers. The Elasticity
buffer may also be centered by a device reset operation
initiated through the TRSTZ input, however, following such an
event the CYP(V)15G0201DXB will normally require a framing
event before it will correctly decode characters. When
RXCKSEL = HIGH, since the Elasticity buffer is not allowed to
insert or delete framing characters, the transmit clocks on all
received channels must all be from a common source.
Dual-channel Bonded Modes
In dual-channel bonded modes (RX Modes 2 and 3, where
RXMODE[1] = HIGH), the associated receive channel pair
Output Registers must be clocked by a common clock. This
mode does not operate when RXCKSEL = MID.
Proper operation in this mode requires that the associated
transmit data streams are clocked from a common reference
with no long-term character slippage between the bonded
channels. In dual-channel mode this means that channels A
and B must be clocked from a common reference.
Prior to the reception of valid data, a Word Sync Sequence (or
that portion of one necessary to align the receive buffers) must
be received on the bonded channels (within the allowable
inter-channel skew window) to allow the Receive Elasticity
Buffers to be centered. While normal characters may be output
prior to this alignment event, they are not necessarily aligned
within the same word boundaries as when they were trans-
mitted.
When RXCKSEL = LOW, both receive channels are clocked
by REFCLK. RXCLKB± outputs are disabled (High-Z), and the
RXCLKA± and RXCLKC+ outputs present buffered and
delayed forms of REFCLK. In this mode, the receive Elasticity
Buffers are enabled. For REFCLK clocking, the Elasticity
Buffers must be able to insert K28.5 characters and delete
framing characters as appropriate. While these insertions and
deletions can take place at any time, they must occur at the
same time on both channels that are bonded together. This is
necessary to keep the data in the bonded channel-pair
properly aligned. This insert and delete process is controlled
by the master channel selected by the RXCLKB+ input as
listed in
Table 14
.
When RXCKSEL = HIGH, the A and B channels are clocked
by the selected recovered clock, as shown in
Table 14
. The
output clock for the channel A/B bonded-pair is output contin-
selected from the recovered clock for channel A or channel B
using the RXCLKB+ input.
Table 14. Dual-Channel Bonded Recovered Clock Select
and Master Channel Select
When data is output using a recovered clock (RXCKSEL =
HIGH), receive channels are not allowed to insert and delete
characters, except as necessary for Elasticity Buffer
alignment.
Power Control
The CYP(V)15G0201DXB supports user control of the
powered up or down state of each transmit and receive
channel. The receive channels are controlled by the RXLE
signal and values present on the BOE [3:0] bus. The transmit
channels are controlled by the OELE signal and the values
present on the BOE[3:0] bus. Powering down unused
channels will save power and reduce system heat generation.
Controlling system power dissipation will improve the system
performance.
Receive Channels
When RXLE = HIGH, the signals on the BOE[3:0] inputs
directly control the power enables for the receive PLLs and
analog circuits. When a BOE[3:0] input is HIGH, the
associated receive channel [A and B] PLL and analog logic are
active. When a BOE[3:0] input is LOW, the associated receive
channel [A and B] PLL and analog logic are powered down.
When RXLE returns LOW, the last values present on the
BOE[3:0] inputs are captured. The specific BOE[3:0] input
signal associated with a receive channel is listed in
Table 9
.
Any disabled receive channel will indicate a constant LFIx
output.
When a disable receive channel is re-enabled, the status of
the associated LFIx output and data on the parallel outputs for
the associated channel may be indeterminate for up to 10 ms.
Table 13. Receive Operating Modes
RX Mode
Mode
Number
[1:0]
0
LL
1
LH
2
HL
3
HH
Operating Mode
Channel
Bonding
Independent
Independent
Dual
Dual
RXMODE
RXSTx Status
Reporting
Status A
Status B
Status A
Status B
RXCLKB+
0
1
Clock Source
RXCLKA±
RXCLKA
RXCLKB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0201DXB-BBC | Dual-channel HOTLink II Transceiver |
| CYV15G0404RB-BGC | Independent Clock Quad HOTLink Reclocking Deserializer |
| CYW15G0101DXB | Single-channel HOTLink II Transceiver(單通道熱連接II收發(fā)器) |
| CYW2315 | Serial Input PLL with 1.2-GHz Prescaler(帶1.2-GHz 預(yù)標(biāo)定器的串聯(lián)輸入PLL) |
| CYW2320 | Serial Input PLL with 2.0-GHz Prescaler(帶2.0-GHz 預(yù)標(biāo)定器的串聯(lián)輸入PLL) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0201DXB-BBI | 制造商:Cypress Semiconductor 功能描述: |
| CYV15G0201DXB-BBXC | 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0201DXB-BBXI | 功能描述:電信線路管理 IC Dual Ch Video IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0203TB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Serializer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。