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參數(shù)資料
| 型號(hào)： | DC178A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC1418 |
| 設(shè)計(jì)資源： | DC178A Design File DC178A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±2.048 V |
| 已用 IC / 零件： | LTC1418 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418IG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418IN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP 更多... |
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20
LTC1418
APPLICATIONS INFORMATION
WU
U
RD = CONVST
CS = 0
BUSY
1418 F18
tCONV
(SAMPLE N)
t6
DATA (N – 1)
DB13 TO DB0
DATA
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA N
DB13 TO DB0
t11
t8
t10
t7
Figure 18. Slow Memory Mode Timing
Figure 19. ROM Mode Timing
RD = CONVST
CS = 0
(SAMPLE N)
BUSY
1418 F19
tCONV
t6
DATA (N – 1)
DB13 TO DB0
DATA
DATA N
DB13 TO DB0
t10
t11
t8
outputs; BUSY goes high releasing the processor and the
processor takes RD (= CONVST) back high and reads the
new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
Serial Output Mode
Serial output mode is selected when the SER/PAR input
pin is high. In this mode, Pins 16 to 20, D0 (EXT/INT), D1
(DOUT), D2 (CLKOUT), D3 (SCLK) and D4 (EXTCLKIN)
assume their serial functions as shown in Figure 20.
(During this discussion these pins will be referred to by
their serial function names: EXT/INT, DOUT, CLKOUT,
SCLK and EXTCLKIN.) As in parallel mode, conversions
are started by a falling CONVST edge with CS low. After a
conversion is completed and the output shift register has
been updated, BUSY will go high and valid data will be
available on DOUT (Pin 19). This data can be clocked out
either before the next conversion starts or it can be clocked
out during the next conversion. To enable the serial data
output buffer and shift clock, CS and RD must be low.
Figure 20 shows a function block diagram of the LTC1418
in serial mode. There are two pieces to this circuitry: the
conversion clock selection circuit (EXT/INT, EXTCLKIN
and CLKOUT) and the serial port (SCLK, DOUT, CS and RD).
Conversion Clock Selection (Serial Mode)
In Figure 20, the conversion clock controls the internal
ADC operation. The conversion clock can be either inter-
nal or external. By connecting EXT/INT low, the internal
clock is selected. This clock generates 16 clock cycles
which feed into the SAR for each conversion.
To select an external conversion clock, tie EXT/INT high
and apply an external conversion clock to EXTCLKIN (Pin
16). (When an external shift clock (SCLK) is used during
a conversion, the SCLK should be used as the external
conversion clock to avoid the noise generated by the
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