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參數(shù)資料
| 型號(hào)： | DC178A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 19/28頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1418 |
| 設(shè)計(jì)資源： | DC178A Design File DC178A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±2.048 V |
| 已用 IC / 零件： | LTC1418 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418IG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418IN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP 更多... |
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26
LTC1418
APPLICATIONS INFORMATION
WU
U
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
G28 SSOP 0694
0.005 – 0.009
(0.13 – 0.22)
0
° – 8°
0.022 – 0.037
(0.55 – 0.95)
0.205 – 0.212**
(5.20 – 5.38)
0.301 – 0.311
(7.65 – 7.90)
12 3
4
5
6 7 8
9 10 11 12
14
13
0.397 – 0.407*
(10.07 – 10.33)
25
26
22 21 20 19 18 17 16 15
23
24
27
28
0.068 – 0.078
(1.73 – 1.99)
0.002 – 0.008
(0.05 – 0.21)
0.0256
(0.65)
BSC
0.010 – 0.015
(0.25 – 0.38)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
allows the user to synchronize the A/D conversion to an
external clock either to have precise control of the internal
bit test timing or to provide a precise conversion time. As in
Figure 24, this mode works when the SCLK frequency is
very low (less than 30kHz). However, the external conver-
sion clock must be between 30kHz and 4.5MHz to maintain
accuracy. If more than 16 SCLKs are provided, more zeros
will be filled in after the data word indefinitely. To select the
external conversion clock tie EXT/INT high. The external
SCLK is applied to SCLK. RD can be used to gate the external
SCLK such that data will clock only after RD goes low.
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