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參數(shù)資料
| 型號(hào)： | DC178A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 16/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC1418 |
| 設(shè)計(jì)資源： | DC178A Design File DC178A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±2.048 V |
| 已用 IC / 零件： | LTC1418 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418IG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418IN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP 更多... |
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23
LTC1418
APPLICATIONS INFORMATION
WU
U
clock and the SCLK. The internal clock has been optimized
for the fastest conversion time, consequently this mode
can provide the best overall speed performance. To select
an internal conversion clock, tie EXT/INT (Pin 20) low. The
internal clock appears on CLKOUT (Pin 18) which can be
tied to SCLK (Pin 17) to supply the SCLK.
Using External Clock for Conversion and Data Transfer.
In Figure 23, data from the previous conversion is output
during the conversion with an external clock providing
both the conversion clock and the shift clock. To select an
external conversion clock, tie EXT/INT high and apply the
Figure 23. External Conversion Clock Selected. Data Transferred During Conversion Using
the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
serial port after transferring the serial output data by
tying it to the RD pin.
Figures 22 to 25 show several serial modes of operation,
demonstrating the flexibility of the LTC1418 serial port.
Serial Data Output During a Conversion
Using Internal Conversion Clock for Conversion and
Data Transfer. Figure 22 shows data from the previous
conversion being clocked out during the conversion with
the LTC1418 internal clock providing both the conversion
D12
D11
D12
CAPTURE ON
RISING CLOCK
D13
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FILL
ZEROS
D13
1
t5
t6
t10
23456789
10
11
12
13
14
15
16
1
2
3
D13
D12
D11
Hi-Z
DATA N
DATA (N – 1)
(SAMPLE N)
(SAMPLE N + 1)
DOUT
CS = 0, EXT/INT = 5
EXTCLKIN (= SCLK)
CONVST
t13
tCONV
t8
SAMPLE
HOLD
tdEXTCLKIN
t7
t11
1418 F23b
BUSY (= RD)
t15
t14
tLEXTCLKIN
tHEXTCLKIN
EXTCLKIN
(= SCLK)
VIL
VOH
VOL
DOUT
CAPTURE ON
FALLING CLOCK
LTC1418
BUSY (= RD)
EXTCLKIN ( = SCLK)
BUSY
CONVST
RD
EXTCLKIN
SCLK
EXT/INT
DOUT
CS
5V
25
20
19
26
24
17
16
23
1418 F23a
P OR DSP
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