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參數(shù)資料
| 型號(hào)： | DC956A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/40頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2485 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC956A Design File DC956A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2485 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2485CDD#TRPBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485IDD#TRPBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485IDD#PBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485CDD#PBF-ND - IC ADC 24BIT I2C 10-DFN |
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LTC2485
19
2485fc
APPLICATIONS INFORMATION
(commonly implemented as a SINC or Comb lter). For
high resolution, low frequency applications, this lter is
typically designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. The lter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2485 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
Frequency Rejection Selection (CA0/f0)
The LTC2485 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip conguration register (the default mode at power-
up is simultaneous 50Hz/60Hz rejection).
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2485 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the CA0/f0 pin and turns off the internal oscilla-
tor. The chip address for CA0 is internally set HIGH. The
frequency fEOSC of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not signicant as long as the minimum and maximum
specications for the high and low periods tHEO and tLEO
are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2485 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
± 4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/5120
is shown in Figure 10.
Figure 10. LTC2485 Normal Mode Rejection
When Using an External Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
–12
–8
–4
0
4
8
12
NORMAL
MODE
REJECTION
(dB)
2485 F10
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
Whenever an external clock is not present at the CA0/f0 pin,
the converter automatically activates its internal oscillator
and enters the Internal Conversion Clock mode. CA0/f0
may be tied HIGH or left oating in order to set the chip
address. The LTC2485 operation will not be disturbed if
the change of conversion clock source occurs during the
sleep state or during the data output state while the con-
verter uses an external serial clock. If the change occurs
during the conversion state, the result of the conversion in
progress may be outside specications but the following
conversions will not be affected.
Table 5 summarizes the duration of the conversion state
of each state and the achievable output data rate as a
function of fEOSC.
Table 5. LTC2485 State Duration
STATE
OPERATING MODE
DURATION
Conversion
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator
CA0/f0 = External Oscillator with
Frequency fEOSC Hz (fEOSC/5120 Rejection)
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s for
1x Speed Mode
20556/fEOSCs, Output Data Rate ≤ fEOSC/20556 Readings/s for
2x Speed Mode
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