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參數資料
| 型號： | DC956A |
| 廠商： | Linear Technology |
| 文件頁數： | 4/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2485 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC956A Design File DC956A Schematic |
| 標準包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數量： | 1 |
| 位數： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數據接口： | I²C，串行 |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2485 |
| 已供物品： | 板 |
| 相關產品： | LTC2485CDD#TRPBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485IDD#TRPBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485IDD#PBF-ND - IC ADC 24BIT I2C 10-DFN LTC2485CDD#PBF-ND - IC ADC 24BIT I2C 10-DFN |
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LTC2485
12
2485fc
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2485 is a low power, ΔΣ analog-to-digital converter
with an I2C interface. After power on reset, its operation
is made up of three states. The converter operating cycle
begins with the conversion, followed by the low power sleep
state and ends with the data output/input (see Figure 1).
Initially, the LTC2485 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read/write opera-
tion. The conversion result is held indenitely in a static
shift register while the converter is in the sleep state.
The device will not acknowledge an external request dur-
ing the conversion state. After a conversion is nished,
the device is ready to accept a read/write request. Once
the LTC2485 is addressed for a read operation, the device
begins outputting the conversion result under control of
the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 32 bits long and contains
a 24-bit plus sign conversion result. This result is shifted
out on the SDA pin under the control of the SCL. Data
is updated on the falling edges of SCL allowing the user
to reliably latch data on the rising edge of SCL. In write
operation, the device accepts one conguration byte and
the data is shifted in on the rising edges of the SCL. A
new conversion is initiated by a STOP condition following
a valid write operation or at the conclusion of a data read
operation (read out all 32 bits).
I2C INTERFACE
The LTC2485 communicates through an I2C interface.
The I2C interface is a 2-wire open-drain interface sup-
porting multiple devices and masters on a single bus.
The connected devices can only pull the bus wires LOW
and they never drive the bus HIGH. The bus wires are
externally connected to a positive supply voltage via a
current-source or pull-up resistor. When the bus is free,
both lines are HIGH. Data on the I2C-bus can be transferred
at rates of up to 100kbit/s in the Standard-mode and up
to 400kbit/s in the Fast-mode. The VCC power should not
be removed from the device when the I2C bus is active to
avoid loading the I2C bus lines through the internal ESD
protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when perform-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. At the same time any device ad-
dressed is considered a slave.
The LTC2485 can only be addressed as a slave. Once ad-
dressed, it can receive conguration bits or transmit the
last conversion result. Therefore the serial clock line SCL
Figure 1. LTC2485 State Transition Diagram
CONVERSION
SLEEP
2485 F01
YES
NO
ACKNOWLEDGE
YES
NO
STOP
OR READ
32-BITS
DATA OUTPUT
POWER ON RESET
DEFAULT CONFIGURATION:
EXTERNAL INPUT
50/60Hz REJECTION
1X SPEED, AUTOCAL
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