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參數(shù)資料
| 型號： | DDP3300A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Display and Deflection Processor |
| 中文描述： | 單芯片顯示器和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 22/53頁 |
| 文件大小： | 1767K |
| 代理商： | DDP3300A |
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DDP 3300 A
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
22
3. Serial Interface
3.1. I
2
C-bus Interface
Communication between the DDP 3300 A and the ex-
ternal controller is done via I
2
C-bus. The DDP 3300 A
has an I
2
C-bus slave interface and uses I
2
C clock syn-
chronization to slow down the interface if required. The
I
2
C-bus interface uses one level of subaddress: one I
2
C-
bus address is used to address the IC and a subaddress
selects one of the internal registers. The I
2
C-bus chip
address is given below:
Note:
The I
2
C address is subject to change!
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
0
1
0/1
The registers of the DDP 3300 A have 8 or 16-bit data
size; 16-bit registers are accessed by reading/writing
two 8-bit data words.
Functions implemented by firmware in the on-chip con-
trol microprocessor (FP) located in the VPC are ex-
plained in the VPC datasheet.
Figure 3–1 shows I
2
C-bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip address
with read command set.
W
P
1 or 2 byte data
W
high byte data
S
S
Ack
Ack
Ack
Ack
0111 1100
0111 1100
R
S
Ack
SDA
SCL
1
0
S
P
P
low byte data
Ack
W =
R
Ack=
Nak=
S
P
0
1
0
1
Start
Stop
=
=
=
Ack
Nak
Fig. 3–1:
I
2
C-bus protocols
1000 101
1000 101
1000 101
I
2
C read access
subaddress 7c
Example:
I
2
C read access
subaddress 7c
3.2. Control and Status Registers
Table 3–1 gives definitions of the DDP 3300 A control
and status registers. The number of bits indicated for
each register in the table is the number of bits imple-
mented in hardware, i.e., a 9-bit register must always be
accessed using two data bytes, but the 7 MSB will be
don’t care on write operations and 0 on read operations.
Write registers that can be read back are indicated in the
following table.
A hardware reset initializes all control registers to 0. The
automatic chip initialization loads a selected set of regis-
ters with the default values given in Table 3–1.
The register modes given in Table 3–1 are:
w
w/r
r
h
v
write only register
write/read data register
read data from DDP 3300 A
register is latched with horizontal pulse
register is latched with vertical pulse
The
DDP 3300 A demo software are given in the last column.
mnemonics
used
in
the
INTERMETALL
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