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參數(shù)資料
| 型號： | DDP3300A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Display and Deflection Processor |
| 中文描述： | 單芯片顯示器和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 27/53頁 |
| 文件大?。?/td> | 1767K |
| 代理商： | DDP3300A |
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DDP 3300 A
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
27
Name
Default
Function
Mode
Number
of bits
I
2
C sub
address
TIMING
67
9
w v
vertical blanking start
bit [8:0]
0..511
first line of vertical blanking
305
VBST
77
9
w v
vertical blanking stop
bit [8:0]
0..511
last line of vertical blanking
25
VBSO
73
9
w v
start of Black Level Expander measurement
bit [8:0]
0..511
first line of measurement, stop with first
line
of vertical blanking
30
AVST
5f
9
w v
bit [8:0] free running field period = (value
4) lines
0
STIMP
HORIZONTAL DEFLECTION
7a
9
w v
adjustable delay of PLL2, clamping, and blanking (relative to
front sync)
adjust clamping pulse for analog RGB input
bit [8:0]
–256..+255
8
μ
s
–141
POFS2
76
9
w v
adjustable delay of flyback, main sync, csync and analog RGB
(relative to PLL2)
adjust horizontal drive or csync
bit [8:0]
–256..+255
8
μ
s
0
POFS3
7e
9
w v
adjustable delay of main sync (relative to flyback)
adjust horizontal position for digital picture
bit [8:0]
20 steps
1
μ
s
120
HPOS
5b
9
w/r
start of horizontal blanking
bit [8:0]
0..511
1
HBST
57
9
w/r
end of horizontal blanking
bit [8:0]
0..511
48
HBSO
6a
6e
72
9
9
9
w v
w v
w v
PLL2/3 filter coefficients, 1 of 5 bit code (n
to 1)
bit [5:0]
proportional coefficient PLL3, 2
–n–1
bit [5:0]
proportional coefficient PLL2, 2
–n–1
bit [5:0]
integral coefficient PLL2, 2
–n–5
bit number set
2
1
2
PKP3
PKP2
PKI2
15
16
w/r
horizontal drive and vertical signal control register
bit [5:0]
0..63
horizontal drive pulse duration in
μ
s
(internally limited to 4..61)
bit [6]
0/1
disable/enable horizontal PLL2 and PLL3
bit [7]
0/1
1: disable horizontal drive pulse during
flyback
bit [8]
0/1
reserved, set to ’0’
bit [9]
0/1
enable/disable ultra black blanking
bit [10]
0/1
0: all outputs blanked
1: normal mode
bit [11]
0/1
enable/disable clamping for analog RGB
input
bit [12]
0/1
disable/enable vertical free running mode
(FIELD is set to field2, no interlace)
bit [13]
0/1
enable/disable vertical protection
bit [14]
0/1
internal/external (under VPC control)
start of vertical and E/W signal
bit [15]
0/1
disable/enable phase shift of display clock
32
0
0
0
0
1
0
0
0
1
HDRV
EHPLL
EFLB
INTRL
DUBL
EBL
DCRGB
SELFT
DVPR
XDEFL
DISKA
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相關(guān)代理商/技術(shù)參數(shù) |
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| DDP3300A(DIP64) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
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| DDP3300A(SDIP64) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| DDP3300AD3 | 制造商:MICRONAS 功能描述:New |
| DDP3300APSD3 | 制造商:MICRONAS 功能描述:New |
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