- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376767 > DM4M32SJ-15 Enhanced DRAM (EDRAM) Module PDF資料下載
參數(shù)資料
| 型號： | DM4M32SJ-15 |
| 英文描述： | Enhanced DRAM (EDRAM) Module |
| 中文描述： | 增強(qiáng)的DRAM（eDRAM內(nèi)存）模塊 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DM4M32SJ-15 |
1-106
Function
/S
Low Power Standby
H
/RE
W/R
/F
A
0-10
Comment
H
X
X
X
Low Power Self
Refresh Option
H = High; L = Low X = Dont Care;
↓
= High-to-LowTransition; LRR = Last RowRead
H
↓
X
H
X
Internal Refresh
X
X
L
X
Read Miss
L
L
H
Row
≠
LRR
DRAM Row to Cache
Write Hit
L
H
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write Miss
L
H
H
Row
≠
LRR
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
Standby Current
Standby Current, Internal Refresh Clock
↓
↓
↓
↓
Read Hit
L
L
H
/CAL
H
L
X
H
H
H
H
/WE
H
Unallowed Mode
H
L
X
H
X
Unallowed Mode (Except -L Option)
X
X
H
X
X
H
H
X
Row = LRR
No DRAM Reference, Data in Cache
↓
EDRAMBasic Operating Modes
Functional Description
The EDRAMis designed to provide optimummemory
performance wth high speed mcroprocessors. As a result, it is
possible to performsimultaneous operations to the DRAMand
SRAMcache sections of the EDRAM This feature allows the EDRAM
to hide precharge and refresh operation during SRAMcache reads
and maximze SRAMcache hit rate by maintaining valid cache
contents during write operations even if data is written to another
memory page. These newfunctions, in conjunction wth the faster
basic DRAMand cache speeds of the EDRAM mnimze processor
wait states.
EDRAMBasic Operating Modes
The EDRAMoperating modes are specified in the table below
Ht andMss Termnology
In this datasheet, “hit” and “mss” always refer to a hit or mss
to the page of data contained in the SRAMcache rowregister. This
is always equal to the contents of the last rowthat was read from
(as modified by any write hit data). Writing to a newpage does not
cause the cache to be modified.
DRAMReadHt
If a DRAMread request is initiated by clocking /RE wth W/R
lowand /F and /CAL high, the EDRAMwll compare the newrow
address to the last rowread address latch (LRR; an 11-bit latch
loaded on each /RE active read cycle). If the rowaddress matches
the LRR, the requested data is already in the SRAMcache and no
DRAMmemory reference is initiated. The data specified by the
column address is available at the output pins at the greater of
times t
AC
or t
GQV
. Since no DRAMactivity is initiated, /RE can be
brought high after time t
RE1
, and a shorter precharge time, t
RP1
, is
required. It is possible to access additional SRAMcache locations
by providing newcolumn addresses to the multiplex address
inputs. Newdata is available at the output at time t
AC
after each
column address change in static column mode. During read cycles,
it is possible to operate in either static column mode wth
/CAL=high or page mode wth /CAL clocked to latch the column
address. In page mode, data valid time is determned by either t
AC
or t
CQV
.
DRAMReadMss
If a DRAMread request is initiated by clocking /RE wth W/R
lowand /F and /CAL high, the EDRAMwll compare the newrow
address to the LRR address latch (an 11-bit latch loaded on each
/RE active read cycle). If the rowaddress does not match the LRR,
the requested data is not in SRAMcache and a newrowmust be
fetched fromthe DRAM The EDRAMwll load the newrowdata
into the SRAMcache and update the LRR latch. The data at the
specified column address is available at the output pins at the
greater of times t
RAC
, t
AC
, and t
GQV
. It is possible to bring /RE high
after time t
RE
since the newrowdata is safely latched into SRAM
cache. This allows the EDRAMto precharge the DRAMarray while
data is accessed fromSRAMcache. It is possible to access
additional SRAMcache locations by providing newcolumn
addresses to the multiplex address inputs. Newdata is available at
the output at time t
AC
after each column address change in static
column mode. During read cycles, it is possible to operate in either
static column mode wth /CAL=high or page mode wth /CAL
clocked to latch the column address. In page mode, data valid
time is determned by either t
AC
or t
CQV
.
DRAMWrite Ht
If a DRAMwrite request is initiated by clocking /RE while W/R
and /F are high, the EDRAMwll compare the newrowaddress to
the LRR address latch (an 11-bit address latch loaded on each /RE
active read). If the rowaddress matches, the EDRAMwll write data
to both the DRAMarray and selected SRAMcache simultaneously
to maintain coherency The write address and data are posted to
the DRAMas soon as the column address is latched by bringing
/CAL lowand the write data is latched by bringing /WE low(both
/CAL and /WE must be high when initiating the write cycle wth the
falling edge of /RE). The write address and data can be latched very
quickly after the fall of /RE (t
RAH
+ t
ASC
for the column address and
t
DS
for the data). During a write burst sequence, the second write
data can be posted at time t
RSW
after /RE. Subsequent writes wthin
a page can occur wth write cycle time t
PC
. Wth /Genabled and
/WE disabled, it is possible to performcache read operations while
the /RE is activated in write hit mode. This allows read-modify-
write, write-verify or randomread-write sequences wthin the page
wth 12ns cycle times (the first read cannot complete until after
time t
RAC2
). At the end of a write sequence (after /CAL and /WE are
brought high and t
RE
is satisfied), /RE can be brought high to
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM4M32SJ-15L | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-12 | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-12L | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-15 | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-15L | Enhanced DRAM (EDRAM) Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM4PRTR | 制造商:Siemens 功能描述: |
| DM4S6B00F/17 | 制造商:NXP Semiconductors 功能描述:DVD-R 16X 100PK Spindle 制造商:NXP Semiconductors 功能描述:DVD-R 16X SPINDLE 100PK |
| DM4S6B25F/17 | 制造商:NXP Semiconductors 功能描述:DVD-R 16X 25PK Spindle 制造商:NXP Semiconductors 功能描述:DVD-R 16X SPINDLE 25PK |
| DM4S6B50F/17 | 制造商:NXP Semiconductors 功能描述:DVD-R 16X 50PK Spindle |
| DM4T1200 | 制造商:Lovato Electric Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。