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參數(shù)資料
| 型號： | DM4M32SJ-15 |
| 英文描述： | Enhanced DRAM (EDRAM) Module |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存）模塊 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DM4M32SJ-15 |
precharge the memory It is possible to performcache reads
concurrently wth precharge. During write sequences, a write
operation is not performed unless both /CAL and /WE are low As a
result, the /CAL input can be used as a byte write select in multi-
chip systems. If /CAL is not clocked on a write sequence, the
memory wll performa /RE only refresh to the selected rowand
data wll remain unmodified.
DRAMWrite Mss
If a DRAMwrite request is initiated by clocking /RE while W/R
and /F are high, the EDRAMwll compare the newrowaddress to
the LRR address latch (an 11-bit latch loaded on each /RE active
read cycle). If the rowaddress does not match, the EDRAMwll
write data to the DRAMarray only and contents of the current
cache is not modified. The write address and data are posted to the
DRAMas soon as the column address is latched by bringing /CAL
lowand the write data is latched by bringing /WE low(both /CAL
and /WE must be high when initiating the write cycle wth the
falling edge of /RE). The write address and data can be latched very
quickly after the fall of /RE (t
RAH
+ t
ASC
for the column address and
t
DS
for the data). During a write burst sequence, the second write
data can be posted at time t
RSW
after /RE. Subsequent writes wthin
a page can occur wth write cycle time t
PC
. During a write mss
sequence, cache reads are inhibited and the output buffers are
disabled (independently of /G) until time t
WRR
after /RE goes high.
At the end of a write sequence (after /CAL and /WE are brought
high and t
RE
is satisfied), /RE can be brought high to precharge the
memory It is possible to performcache reads concurrently wth
the precharge. During write sequences, a write operation is not
performed unless both /CAL and /WE are low As a result, /CAL can
be used as a byte write select in multi-chip systems. If /CAL is not
clocked on a write sequence, the memory wll performa /RE only
refresh to the selected rowand data wll remain unmodified.
/RE Inactive Operation
It is possible to read data fromthe SRAMcache wthout
clocking /RE. This option is desirable when the external control
logic is capable of fast hit/mss comparison. In this case, the
controller can avoid the time required to performrow/column
multiplexing on hit cycles. This capability also allows the EDRAMto
performcache read operations during precharge and refresh
cycles to mnimze wait states. It is only necessary to select /S and
/Gand provide the appropriate column address to read data as
shown in the table below The rowaddress of the SRAMcache
accessed wthout clocking /RE wll be specified by the LRR address
latch loaded during the last /RE active read cycle. To performa
cache read in static column mode, /CAL is held high, and the cache
contents at the specified column address wll be valid at time t
AC
after address is stable. To performa cache read in page mode,
/CAL is clocked to latch the column address. The cache data is
valid at time t
AC
after the column address is setup to /CAL.
On-ChpSRAMInterleave
The DM4M32 has an on-chip interleave of its SRAMcache
which allows 8ns randomaccesses (t
AC1
) for up to three data
words (burst reads) followng an initial read access (hit or mss).
The SRAMcache is integrated into the DRAMarrays in a 512 x 128
organization. It is converted into a 2K x 32 page organization by
using an on-chip address multiplexer to select one of four 32-bit
words to the output pins DQ
0-31
(as shown below). The specific
word selected to the output is determned by column addresses A
o
and A
1
. Systemoperation is consistent wth the standard
“Functional Description” and timng diagrams shown in this
specification. See the note in the read timng diagrams and
“Swtching Characteristics” chart for the faster access and data
hold times.
DM4M32 DatapathArchtecture
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the rowaddress supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles during which /S can be disabled.
/CAL Before /RE Refresh(“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below
/RE Ony RefreshOperation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAMrefresh, it is possible to perform
an /RE only refresh using an externally supplied rowaddress. /RE
refresh is performed by executing a
write cycle
(W/R and /F are
high) where /CAL is not clocked. This is necessary so that the current
cache contents and LRR are not modified by the refresh operation.
All combinations of addresses A
0
, A
2
- A
10
must be sequenced every
64ms refresh period. A
1
does not need to be cycled. Read refresh
cycles are not allowed because a DRAMrefresh cycle does not occur
when a read refresh address matches the LRR address latch.
1-107
Function
/S
/G
/CAL
A
0-10
Cache Read (Static Column)
L
H
Column Address
Cache Read (Page Mode)
L
¤
Column Address
H = High; L = Low X = Dont Care;
¤
= Transitioning
L
L
65,538 Bits
128 Bits
32 Bits
Q
Row Address
A
0-10
Column Address
A
2-10
Column Address
A
0,
A
1
32
4M DRAM Arrays
32
2K SRAM Caches
4 to 1
Output Selector
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM4M32SJ-15L | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-12 | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-12L | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-15 | Enhanced DRAM (EDRAM) Module |
| DM4M32SJ6-15L | Enhanced DRAM (EDRAM) Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM4PRTR | 制造商:Siemens 功能描述: |
| DM4S6B00F/17 | 制造商:NXP Semiconductors 功能描述:DVD-R 16X 100PK Spindle 制造商:NXP Semiconductors 功能描述:DVD-R 16X SPINDLE 100PK |
| DM4S6B25F/17 | 制造商:NXP Semiconductors 功能描述:DVD-R 16X 25PK Spindle 制造商:NXP Semiconductors 功能描述:DVD-R 16X SPINDLE 25PK |
| DM4S6B50F/17 | 制造商:NXP Semiconductors 功能描述:DVD-R 16X 50PK Spindle |
| DM4T1200 | 制造商:Lovato Electric Inc 功能描述: |
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