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參數(shù)資料
| 型號： | DM4M32SJ-15 |
| 英文描述： | Enhanced DRAM (EDRAM) Module |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存）模塊 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 164K |
| 代理商： | DM4M32SJ-15 |
1-108
Low Power Self Refresh
When the lowpower, self-refresh option is specified when
ordering the EDRAM the EDRAMenters this mode when /RE is
clocked while /S, W/R, /F and /WE are high; and /CAL is low In
this mode, the power is turned off to all I/Opins except /RE to
mnimze chip power and an on-board refresh clock is enabled to
performself-refresh cycles using the on-board refresh counter.
The EDRAMremains in this lowpower mode until /RE is brought
high again to termnate the mode. The EDRAM/RE input must
remain high for t
RP2
followng exit fromself-refresh mode to allow
any on-going internal refresh to termnate prior to the next
memory operation.
Low Power Mode
The EDRAMenters its lowpower mode when /S is high. In this
mode, the internal DRAMcircuitry is powered down to reduce
standby current to 34mA.
IntializationCycles
A mnimumof 10 initialization (start-up) cycles are required
before normal operation is guaranteed. A combination of eight /F
refresh cycles and two read cycles to different rowaddresses are
necessary to complete initialization. /RE must be high for 300ns
prior to initialization.
UnallowedMode
Read, write, or /RE only refresh operations must not be
initiated to unselected memory banks by clocking /RE when /S is
high.
ReducedPinCount Operation
It is possible to simplify the interface to the 16 MByte SIMMto
reduce the number of control lines. /REOand /RE2 could be tied
together externally to provide a single rowenable. W/R and /Gcan
be tied together if reads are not performed during write hit cycles.
This external wring simplifies the interface wthout any
performance impact.
PinDescriptions
/RE
0, 2
— Row Enabe
These inputs are used to initiate DRAMread and write
operations and latch a rowaddress as well as the states of W/R and
/F It is not necessary to clock /RE
0, 1
to read data fromthe EDRAM
SRAMrowregisters. On read operations, /RE
0, 1
can be brought
high as soon as data is loaded into cache to allowearly precharge.
/REOcontrols Bytes 1 and 2. /RE2 controls Bytes 3 and 4.
/CAL
0 -3
— ColumnAddress Latch
These inputs are used to latch the column address and in
combination wth /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low
the column address is closed and the output of the latch contains
the address present while /CAL was high. /CAL can be toggled when
/RE is lowor high. However, /CAL must be high during the high-to-
lowtransition of /RE except for /F refresh cycles. /CAL
0-3
controls
Bytes 1-4 respectively
W/R — Write/Read
This input along wth /F specifies the type of DRAMoperation
initiated on the lowgoing edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
/F — Refresh
This input wll initiate a DRAMrefresh operation using the
internal refresh counter as an address source when it is lowon the
lowgoing edge of /RE.
/WE — Write Enabe
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low
/G— Output Enabe
This input controls the gating of read data to the output data
pins during read operations.
/S — ChpSelect
This input is used to power up the I/Oand clock circuitry
When /S is high, the EDRAMremains in its lowpower mode. /S
must remain active throughout any read or write operation. Wth
the exception of /F refresh cycles, /RE
0,2
should never be clocked
when /S is inactive.
DQ
0 -31
— Data Input/Output
These bidirectional pins are used to read and write data to the
EDRAM
PD— Presence Detect
This signal is grounded to indicate the presence of SIMM
module in the socket.
PD16M— 16MPresence Detect
This signal is grounded to indicate the presence of a 16M
SIMM A 4 or 8 MB SIMMhas this pin open.
A
0-10
— Mutipex Address
These inputs are used to specify the rowand column
addresses of the EDRAMdata. The 11-bit rowaddress is latched on
the falling edge of /RE. The 11-bit column address can be specified
at any other time to select read data fromthe SRAMcache or to
specify the write column address during write cycles. A
0,1
are used
to select one of four interleaved data words during read
operations.
V
CC
Power Suppy
These inputs are connected to the +5 volt power supply
V
SS
Ground
These inputs are connected to the power supply ground
connection.
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