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參數(shù)資料
| 型號(hào)： | DM6588F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | V.90 Intergrated Data/Fax/Voice/Speakephone Modem Device Single Chip with Memory Built in |
| 中文描述： | .90綜合數(shù)據(jù)/傳真/語(yǔ)音/ Speakephone調(diào)制解調(diào)器設(shè)備的單芯片，具有內(nèi)置的記憶 |
| 文件頁(yè)數(shù)： | 12/43頁(yè) |
| 文件大?。?/td> | 292K |
| 代理商： | DM6588F |
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DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
12
Preliminary
Version: DM562P-DS-P02
February 28, 2001
HDLC TxFiFo Register: Address DC03H
Write only
The original HDLC frame data will be loaded to the
TxFIFO, presented to the input of the TxHDLC circuit.
The TxFIFO is 21 bytes wide.
HDLC TxBuffer: Address DC03H
Read only
According to TxDataBits, the TxHDLC circuit will
transfer the same number data bits to the TxBuffer.
The TxBuffer is 16 bytes wide.
HDLC CNTL/STATUS Register: Address DC04H
Bit0:TxReady0
0: indicates the data in the TxFIFO has
deceased to zero and the HDLC circuit has
transferred the 1
st
7eH pattern.
1:indicates that the TxFIFO data is greater than
or equal to the threshold value.
Bit1:Rxdata
0: all the data in the RxBuffer has been read.
1:Programed by software to indicate that all data in
the RxDataBits register has been written to the
RxBuffer.
Bit2:TxFIFO Threshold
0: TxFIFO threshold No. = 11
1: TxFIFO threshold No. =16
Bit3:TxFiFo Status
0:data No. in TxFIFO >= threshold
1:data No. in TxFIFO <= threshold
Bit4:Txdata
0:A write action to TxDataBites register will clear
this bit.
1:Bit No. in TxBuffer = TxDataBits register.
Bit5: RxFIFO empty
0:data bytes No. in RxFIFO <>0
1:data bytes No. in RxFIFO = 0
Bit6: Reset
0:Normal state
1:reset HDLC circuit
Zero Deletion In
_
buffer register: Address DC08H
write only
Controller write the original data to this temp buffer.
Zero Deletion Out
_
buffer register: Address
DC08H
read only
Controller read the result data from this buffer
Zero Deletion Status/Rst register: Address DC09H
Bit0: data ready flag (read only)
1:data has been load to out
_
buffer. (clear
automatically by a read from out
_
buffer)
0: data has not been load to out
_
buffer.
Bit1: frame end flag (read only)
1:Indicate end of HDLC frame (clear by a reset
action)
Bit2: fram ready flag (read only)
1:CRC check ok.
0:CRC check fail.
Bit3: In
_
buffer empty flag
1:In
_
buffer empty (clear automatically by a
write to In
_
buffer)
0:In
_
buffer not empty
Bit7: reset bit (write only)
1:software reset
(4)CRCL register: Address DC0AH (read only)
(5)CRCH register: Address DC0BH (read only)
UART (16550A) Emulation Registers (pci only)
Receiver Buffer (Read), Transmitter Holding
Register (Write):
Address: 0 (DLAB=0)
Reset State 00h
bit7
bit6
dat7
dat6
bit5
dat5
bit4
dat4
bit3
dat3 Dat2 dat1 Dat0
Bit2
bit1
Bit0
When this register address is read, it contains the
parallel received data. Data to be transmitted is
written to this register.
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