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參數(shù)資料
| 型號(hào)： | DM6588F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | V.90 Intergrated Data/Fax/Voice/Speakephone Modem Device Single Chip with Memory Built in |
| 中文描述： | .90綜合數(shù)據(jù)/傳真/語(yǔ)音/ Speakephone調(diào)制解調(diào)器設(shè)備的單芯片，具有內(nèi)置的記憶 |
| 文件頁(yè)數(shù)： | 6/43頁(yè) |
| 文件大?。?/td> | 292K |
| 代理商： | DM6588F |
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DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
6
Preliminary
Version: DM562P-DS-P02
February 28, 2001
according to the rising edge of SCLK. The MSB is
sent immediately after the falling edge of the
FR_SP1 signal.
Bank Switch Control:
These signals are used to switch external program
memory between banks.
CA16 CA17
Bank 0 0 0
Bank 1 1 0
Bank 2 0 1
Bank 3 1 1
Controller Counter 0 Input
Controller Counter 1 Input
Ring Signal Input
TxDSP Interrupt 1 Input (PCI)
DTR Input Pin (P1.1)
Hook Relay Control (P1.2)
Voice Relay Control. Modem Control Output
(memory map is bit 3 of DAA at memory address
D000H)
EEPROM Control Pins (P1.4-P1.6)
Loop Current Detection. Modem Input Control:
This pin is mapped to bit0 of address D000H.
Reference Clock For Serial Port 1 And Serial
Port 2 (PCI)
Controller Serial Port Data Input
Controller Serial Port Data Output
Data Input Pin Of The Serial Port 2 (PCI)
The serial data is sampled at the falling edge of the
SCLK. The MSB is coming immediately after the
falling of FR_SP2 signal.
Data Input Pin Of The Serial Port 1 (PCI)
The serial data is sampled at the falling edge of the
SCLK. The MSB is coming immediately after the
falling of FR_SP1 signal.
49
47
49
47
CA16
CA17
O
51
52
57
T0
T1
/RI
I
I
I
I
I
57
58
59
60
TxSCLK*2
/DTR
/OH
/VOICE
58
59
60
O
O
61-63
61-63
66
EEPROM 1-3
/LCS
I/O
I
66
SCLK
I
68
69
RXD
TXD
RD_SP2
I
O
I
68
69
RD_SP1
I
70
70
RxSCLK
I
Rx DSP Interrupt 3 Input
Controller Program Store Enable:
This output goes low during a fetch from external
program memory.
Controller External Data Memory Write Control
Controller External Data Memory Read Control
TxDSP Interrupt 3 Input (External)
Modem Received Data (External)
Shifted out to the EIA port through this pin
according to the rising edge of RXDCLK.
Reference Clock For Serial Port 1 And Serial
Port 2 (External)
Test pin 1, normal ground
71
71
/PSEN
O
72
73
72
73
76
78
/WR
/RD
O
O
I
O
TxSCLK*2
DSPRxD
79
SCLK
I
117
117
TEST1
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