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參數(shù)資料
| 型號： | DM8108 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8 port 10/100M Fast Ethernet Switching Controller |
| 中文描述： | 8端口10/100M快速以太網(wǎng)交換控制器 |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 371K |
| 代理商： | DM8108 |
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DM8108
8 port 10/100M Fast Ethernet Switching Controller
14
Preliminary
Version: DM8108-DS-P02
November 25, 1999
Media Access Control
The MAC Engine incorporates the essential protocol
requirement for an Ethernet IEEE-802.3 compliant
node, and provides the interface between the FIFO
subsystem and the MII. The MAC has two primary
attributes:
Transmit and receive message data
encapsulation
The MAC will discard the illegally short (less than 64
bytes of frame data) or oversized (greater than 1536
bytes) messages to be transmitted or received.
Framing (frame boundary delimitation, frame
synchronization)
The MAC engine will automatically handle the
construction of the transmit frame. Once the
transmit FIFO has been filled to the predetermined
threshold and access of the channel is permitted, the
MAC will commence the following for transmission:
The receiving section of the MAC will detect an
incoming preamble sequence when the RXDV signal
is activated by the external PHY. The MAC will
discard the preamble and begin searching for the SFD.
Once the SFD is detected, all the subsequent nibbles
are treated as part of the frame. The MAC will discard
the message if it is shorter than 64-bytes or longer
than 1518 (1536) bytes. The received frame will be
sent to Receiving Buffer for switching.
If the frame terminates or suffers a collision before
64-bytes (after SFD) have been received, the MAC
will automatically delete the frame from FIFO.
Addressing (source and destination address
handling)
The MAC intercepts the source and destination
address from the incoming frame and send them
to switching engine for the following purposes:
. To update the address table
. To learn the switching target
. To detect the DM8108 predefined address for
the device control functions.
Error detection (physical medium transmission
errors)
During transmission, if the switching engine
failed to keep the transmit FIFO filled sufficiently,
cause an underflow, the MAC engine will
guarantee the message is either sent as runt
packet (which will be detected by the receiving
station) or as an invalid FCS (which will cause
the receiver to reject the packet).
During reception, the FCS is generated on every
nibble (including the dribbling bits) coming from
the cable, although the internally saved FCS
value is only updated on the eighth bit (on each
byte boundary). The MAC engine will ignore up
to 7 additional bits at the end of a message
(dribbling bits), that can occur under normal
network operating conditions.
Preamble
1010…1010
7
Bytes
SFD
10101011
1
Bytes
Destination
Address
6
Bytes
Source
Address
6
Bytes
Length
Data
FCS
2
Bytes
40 – 1500
Bytes
4
Bytes
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| DM8121W | 8-Input Digital Multiplexer |
| DM8123N | 2-Input Digital Multiplexer |
| DM7123J | 2-Input Digital Multiplexer |
| DM7123W | 2-Input Digital Multiplexer |
| DM8123W | 2-Input Digital Multiplexer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM-810A | 功能描述:數(shù)字萬用表 DMM,TRMS 1000V AC/DC 600mA to 10A RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類型:Bench 準確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測距: 真均方根值: 數(shù)據(jù)保持: |
| DM-810A-C | 功能描述:數(shù)字萬用表 DMM,TRMS 1000V AC/DC 600mA to 10A, CALIB RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類型:Bench 準確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測距: 真均方根值: 數(shù)據(jù)保持: |
| DM8121J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Input Digital Multiplexer |
| DM8121N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Input Digital Multiplexer |
| DM8121N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Input Digital Multiplexer |
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