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參數(shù)資料
| 型號(hào)： | DM8108 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8 port 10/100M Fast Ethernet Switching Controller |
| 中文描述： | 8端口10/100M快速以太網(wǎng)交換控制器 |
| 文件頁(yè)數(shù)： | 16/35頁(yè) |
| 文件大小： | 371K |
| 代理商： | DM8108 |
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DM8108
8 port 10/100M Fast Ethernet Switching Controller
16
Preliminary
Version: DM8108-DS-P02
November 25, 1999
10/100 Mbps MII Half–duplex Transmission
When the MAC has a frame ready for transmission, it
samples the link activity. If the CRS signal is inacive
(no activity on the link), and the IPG counter has
expired, frame transmission begins. The data is
transmitted through TxD(3:0) of the transmitting port,
clocked on the rising edge of TxCLK. The TxEN is
asserted at same time. In case of collision, the PHY
asserts the COL signal on the MAC, which will then
stop the transmission and will perform contention
resolution. The retry policy is based on the:
Transmit Exception Conditions
Under normal operating conditions
The MAC will ensure that the collisions that
occurred within 512 bit times from the start of
transmission (including preamble) to be
automatically retried with no switching engine
intervention. The transmit FIFO ensures this by
guaranteeing that the data contained within the
FIFO will not be overwritten until at least 64
bytes (512 bits) of preamble plus address, length,
and data fields have been transmitted onto the
network without encountering a collision. In full-
duplex mode, the data in the FIFO can be
overwritten as soon as it is transmitted.
Under abnormal operating conditions
. Late collision
The MAC will abandon the transmit process for
that frame, and process the next transmit frame
in the ring. Frame experiencing a late collision
will not be retried.
TxCLK
TxEN,
TxD(3:0)
0ns – 25ns
10/100 Mbps MII Half-duplex Reception
Frame reception starts with the assertion of RxDV
(while the MAC is not transmitting) by the PHY.
Once RxDV is asserted, the MAC will begin sampling
the incoming data on pins RxD(3:0) on the rising edge
of RxCLK. Reception ends when the RxDV is de-
asserted by the PHY. The last nibble sampled by the
MAC is the nibble present on RxD(3:0) on the last
RxCLK rising edge in which RxDV is still asserted. If
MAC detected the assertion of RxER while RxDV is
asserted, it will designate this packet as corrupted.
The following figure shows the MII receive signals
timing.
10ns min.
RxCLK
RxDV, RxER, RxD(3:0)
10ns min.
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| DM-810A | 功能描述:數(shù)字萬(wàn)用表 DMM,TRMS 1000V AC/DC 600mA to 10A RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類型:Bench 準(zhǔn)確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計(jì)數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測(cè)距: 真均方根值: 數(shù)據(jù)保持: |
| DM-810A-C | 功能描述:數(shù)字萬(wàn)用表 DMM,TRMS 1000V AC/DC 600mA to 10A, CALIB RoHS:否 制造商:Tektronix 產(chǎn)品:Multimeters 類型:Bench 準(zhǔn)確性:0.04 % 電壓范圍:2 V to 2 kV 電阻范圍: 電容范圍: 顯示計(jì)數(shù): 頻率:10 Hz to 45 Hz, 850 Hz to 1 MHz 測(cè)距: 真均方根值: 數(shù)據(jù)保持: |
| DM8121J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Input Digital Multiplexer |
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| DM8121N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Input Digital Multiplexer |
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