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參數(shù)資料
| 型號(hào)： | DM9008F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA/Plug & Play Super Ethernet Contoller |
| 中文描述： | 的ISA /插頭 |
| 文件頁數(shù)： | 22/68頁 |
| 文件大?。?/td> | 403K |
| 代理商： | DM9008F |
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DM9008
ISA/Plug & Play Super Ethernet Contoller
22
Final
Version :DM9008-DS-F02
June 14, 2000
Interrupt Status Register (ISR)
This register is accessed to determine the cause of an
interrupt. Any interrupt can be masked in the interrupt Mask
Register (IMR). Individual interrupt bits are cleared by writing a
1 to the corresponding bit of the ISR.
The IRQ signal is active as long as any unmasked signal is set,
and will not go low until all unmasked bits in this register have
been cleared.
The ISR must be cleared after power up by writing it with all
1's.
7
6
5
4
3
2
1
0
RST
RDC
CNT
OVW
TXE
RXE
PTX
PRX
Bit
Symbol
Description
D0
PRX
Packet Received: lndicates packet received with no errors
D1
PTX
Packet Transmitted: lndicates packet transmitted with no errors
D2
RXE
Receive Error: lndicates that a packet was received with one or more of the following errors:
-- CRC Error
-- Frame Alignment Error
-- FIFO Overrun
-- Missed Packet
D3
TXE
Transmit Error: Set when packet is transmitted with one or more of the following errors:
-- Excessive Collisions
-- FIFO Underrun
D4
OVW
Overwrite Warning: Set when receive buffer ring storage resources have been exhausted.
(Local DMA has reached Boundary Pointer.)
D5
CNT
Counter Overflow: Set when MSB of one or more of the Network Tally Counters has been set
D6
RDC
Remote DMA Complete: Set when Remote DMA operation has been completed
D7
RST
Reset Status: A status indicator (no interrupt generated):
-- Set when ENC enters reset state and cleared when a start command is issued.
-- Set when a Receive Buffer Ring overflows and cleared when overflow status ends
Writing to this bit has no effect. The bit powers up high
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