參數(shù)資料
型號： DM9008F
廠商： Electronic Theatre Controls, Inc.
英文描述： ISA/Plug & Play Super Ethernet Contoller
中文描述： 的ISA /插頭
文件頁數(shù)： 45/68頁
文件大小： 403K
代理商： DM9008F
DM9008
ISA/Plug & Play Super Ethernet Contoller
Bus Arbitration and Timing
Final
Version :DM9008-DS-F02
June 14, 2000
45
Alignment of the Received Packet in the FIFO
Reception of the packet in the FIFO begins at location zero.
After the FIFO pointer reaches the last location in the FIFO, the
pointer wraps to the top of the FIFO, overwriting the previously
received data. This process continues until the last byte is
received. The ENC then appends the received byte count in
the next two locations of the FIFO. The value of the next FIFO
location is 0. The number of bytes used in the loopback packet
determines the alignment of the packet in the FIFO. The
alignment for a 64-byte packet is shown below.
FIFO LOCATION
FIFO CONTENTS
0
LOWER BYTE COUNT
1
UPPER BYTE COUNT
2
0
3
LAST BYTE
4
CRC1
5
CRC2
6
CRC3
7
CRC4
For the following alignment in the FIFO, the packet length
should be (N x 8) + 5 bytes. Note that if the CRC bit in TCR is
set, CRC will not be appended by the transmitter. If CRC is
appended by the transmitter, the last four bytes, bytes N-3 to
N, will correspond to the CRC.
FIFO LOCATIONFIFO CONTENTS
0
BYTE N-4
1
BYTE N-3 (CRC1)
2
BYTE N-3 (CRC2)
3
BYTE N-3 (CRC3)
4
BYTE N (CRC4)
5
LOWER BYTE COUNT
6
UPPER BYTE COUNT
7
0
DM9008 powers up as a bus slave in the Reset state, in which
the receiver and transmitter are both disabled. The reset state
can be reentered under three conditions: soft reset (Stop
Command) hard reset (RST input or PC RESET por
command), or an error that shuts down the receiver or
transmitter (FIFO underflow or overflow, receive buffer ring
overflow). After initialization of registers, DM9008 is issued a
Start Command, causing it to enter idle state. Until the DMA is
required, DM9008 remains idle. Idle state is exited by a
request from FIFO in the case of a receive, transmit or a
request from the remote DMA in the case of a remote DMA
operation.
After the remote or local DMA transfer is completed, DM9008
again enters the idle state.
FIFO Burst Control
All local DMA transfers are burst transfers. Once the DMA is
activated, it will transfer an exact burst of bytes programmed in
the DCR. If there are remaining bytes in the FIFO, the next
burst will not be initiated until the FIFO threshold is exceeded.
Interleaved Local Operation
If a remote DMA transfer is initiated or in progress when a
packet is being received or transmitted, the remote DMA
transfer will be interrupted for higher priority local DMA
transfers. When the local DMA transfer is completed, the
remote DMA will rearbitrate for the bus and continue its
transfers. Note that if the FIFO requires service while a remote
DMA is in progress, the local DMA burst is appended to the
remote transfer.
相關(guān)PDF資料
PDF描述
DM9081 10BASE-T Hub Controller
DM9081F 10BASE-T Hub Controller
DM9095 Twisted-Pair Medium Attachment Unit
DM9095L Twisted-Pair Medium Attachment Unit
DM9102D SINGLE CHIP FAST ETHEMET NIC CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9009CJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate
DM9009CN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 4-input NAND Gate
DM9010 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Ethernet Controller with General Processor Interface
DM9010_06 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Single Chip Ethernet Controller with General Processor Interface
DM9010B 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Single Chip Ethernet Controller With General Processor Interface
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*