參數(shù)資料
型號(hào)： DM9102AT
廠商： Electronic Theatre Controls, Inc.
英文描述： Single Chip Fast Ethernet NIC controller
中文描述： 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁(yè)數(shù)： 7/77頁(yè)
文件大?。?/td> 459K
代理商： DM9102AT
DM9102A
Single Chip Fast Ethernet NIC controller
Final
Version: DM9102A-DS-F03
August 28, 2000
7
Pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power,
LI = reset Latch Input, # = asserted Low
PCI Bus and CardBus Interface Signals
Pin No.
128QFP/128TQFP
113
Pin Name
I/O
Description
INT#
O/D
Interrupt Request
This signal will be asserted low when an interrupt condition
as defined in CR5 is set, and the corresponding mask bit in
CR7 is not set.
System Reset
When this signal is asserted low, DM9102A performs the
internal system reset to its initial state.
PCI system clock
PCI bus clock that provides timing for DM9102A related to
PCI bus transactions. The clock frequency range is up to
40MHz.
Bus Grant
This signal is asserted low to indicate that DM9102A has
been granted ownership of the bus by the central arbiter.
Bus Request
The DM9102A will assert this signal low to request the
ownership of the bus.
Power Management Event.
Open drain. Active Low. The DM9102A drive it low to
indicates that a power management event has occurred.
Initialization Device Select
This signal is asserted high during the Configuration Space
read/write access.
Cycle Frame
This signal is driven low by the DM9102A master mode to
indicate the beginning and duration of a bus transaction.
Initiator Ready
This signal is driven low when the master is ready to
complete the current data phase of the transaction. A data
phase is completed on any clock both IRDY# and TRDY#
are sampled asserted.
Target Ready
This signal is driven low when the target is ready to complete
the current data phase of the transaction. During a read, it
indicates that valid data is asserted. During a write, it
indicates the target is prepared to accept data.
Device Select
The DM9102A asserts the signal low when it recognizes its
target address after FRAME# is asserted. As a bus master,
the DM9102A will sample this signal that insures its
114
RST#
I
115
PCICLK
I
117
GNT#
I
118
REQ#
O
119
PME#
O/D
3
IDSEL
I
21
FRAME#
I/O
23
IRDY#
I/O
24
TRDY#
I/O
26
DEVSEL#
I/O
相關(guān)PDF資料
PDF描述
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
DM9108APPLICATIONENGINEERINGNOTESTWO DM9108 Application Engineering notes two
DM9161A 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
DM9161AE 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102DEP 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes
DM9102H 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102HEP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
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