參數(shù)資料
型號: DM9102DE
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁數(shù): 29/70頁
文件大?。?/td> 2245K
代理商: DM9102DE
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
29
31
30
29 28 27 26
25 24
23
22 21 20 19 18
17 16
15
14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
Bit
31
30
29
28:27
26
25
24
23
Name
MDIX
MFUN
LEDM
Reserved
FDX
LNK100
LNK10
RSTPHY
Default
0,RO
0,RO
0,RO
0,RO
X,RO
X,RO
X,RO
0,RW
Description
Status of disable auto-MDIX function
Multi-function strap pin status
LED mode strap pin status
Reserved
Full-duplex status of internal PHY.
100M link status of internal PHY.
10M link status of internal PHY
PHY Reset
Write 1 to this bit will reset internal PHY.
Reserved
Load EEPROM status
It is set to indicate the load of EEPROM is in progress.
Reload EEPROM
Set to reload the content of EEPROM.
MII Management Data_In
This is a read-only bit to indicate the MDIO input data, when bit 18 MRW is set.
MII Management Read/Write Mode Selection
This bit defines the Read/Write Mode for PHY MII management register access. 1
for read and 0 for write.
MII Management Data_Out
This bit is used to generate the output data signal for PHY MII management register
access.
MII Management Clock
This bit is used to generate the output clock signal for PHY MII management
register access.
Reserved.
EEPROM Selected
This bit is used to enable EEPROM access.
Reserved
Reserved
Data_Out from EEPROM
This bit reflects the status of EEDI pin when the EEPROM access is enabled.
22
21
Reserved
LES
0,RO
0,RO
20
RLM
0,RW
19
MDIN
0,RO
18
MRW
0,RW
17
MDOUT
0,RW
16
MDCLK
0,RW
15:12
11
Reserved
ERS
1000,RO
0,RW
10:8
7:4
3
Reserved
Reserved
CRDOUT
011,RW
FH,RO
0,RW
2
CRDIN
0,RW
Data_In to EEPROM
This bit maps to EEDO pin when the EEPROM access is enabled.
Clock to EEPROM
This bit maps EECK pin when the EEPROM access is enabled
Chip_Select to EEPROM
This bit maps to EECS pin when the EEPROM access is enabled
1
CRCLK
0,RW
0
CRCS
0,RW
6.2.11 PHY Status Register (CR12)
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