參數(shù)資料
型號(hào)： DM9102DE
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述： 單晶片快速以太網(wǎng)NIC控制器
文件頁數(shù)： 45/70頁
文件大小： 2245K
代理商： DM9102DE
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
45
Bit 1: FUE, FIFO Underrun Error
It is set to indicate that the transmission aborted due to
transmit FIFO underrun condition.
TDES1: Transmit buffer control and buffer size
Bit 0: DF, Deferred
It is set to indicate that the frame is deferred before ready to
transmit.
31
30
29
28
27
26
25
24
23
22
21 ~ 11
10 ~ 0
CI
ED
BD
FMB1 SETF CAD
///
CE
PD FMB0
Buffer Length
Bit 31: CI, Completion Interrupt
It is set to enable transmit interrupt after the present frame
has been transmitted. It is valid only when TDES1<30> is
set or when it is a setup frame.
Bit 30: ED, Ending Descriptor
It is set to indicate the pointed buffer contains the last
segment of a frame.
Bit 29: BD, Begin Descriptor
It is set to indicate the pointed buffer contains the first
segment of a frame.
Bit 28: FMB1, Filtering Mode Bit 1
This bit is used with FMB0 to indicate the filtering type when
the present frame is a setup frame.
Bit 27: SETF, Setup Frame
It is set to indicate the current frame is a setup frame.
Bit 26: CAD, CRC Append Disable
It is set to disable the CRC appending at the end of the
transmitted frame. Valid only when TDES1<29> is set.
Bit 24: CE, Chain Enable
Must be “1”.
Bit 23: PD, Padding Disable
TDES2: Buffer Starting Address indicates the physical starting address of buffer.
31
This bit is set to disable the padding field for a packet shorter
than 64 bytes.
Bit 22: FMB0, Filtering Mode Bit 0
This bit is used with FMB1 to indicate the filtering type when
the present frame is a setup frame.
FMB1 FMB0 Filtering Type
0 0 Perfect Filtering
0 1 Hash Filtering
1 0 Inverse Filtering
1 1 Hash-Only Filtering.
Bit 21:
IP Packet Checksum Generation
This bit is set to enable the IP packet checksum generation,
if per-packet checksum in CR15 bit 31 is enabled
Bit 20: TCP Packet Checksum Generation
This bit is set to enable the TCP packet checksum
generation, if per-packet checksum in CR15 bit 31 is
enabled.
Bit 19: UDP Packet Checksum Generation
This bit is set to enable the UDP packet checksum
generation, if per-packet checksum in CR15 bit 31 is
enabled.
Bit 10-0: Buffer 1 length
Indicates the size of buffer in Chain type structure.
TDES3: Address indicates the next descriptor starting address
Indicates the physical starting address of the chained descriptor under the Chain descriptor structure.
This address must be eight-word alignment.
0
Buffer Address 1
相關(guān)PDF資料
PDF描述
DM9102 Single Chip Fast Ethernet NIC controller
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102DEP 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes
DM9102H 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102HEP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9103 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface
DM9103EP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Three Port Ethernet Switch Controller with PCI Interface
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