參數(shù)資料
型號: DM9102DE
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁數(shù): 38/70頁
文件大小: 2245K
代理商: DM9102DE
38
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
1
SLEEP
0,RW
Sleep Mode:
Writing a 1 to this bit will cause PHY entering the Sleep mode and power
down all circuit except oscillator and clock generator circuit. When waking up
from Sleep mode (write this bit to 0), the configuration will go back to the state
before sleep; but the state machine will be reset.
Remote Loop out Control:
When this bit is set to 1, the received data will loop out to the transmit channel.
This is useful for testing bit error rate.
0
RLOUT
0,RW
6.3.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
Bit
Name
Default
15
100FDX
1, RO
Description
100M Full Duplex Operation Mode:
After Auto-negotiation is completed, results will be written to this bit. If this bit is
1, it means the operation mode is a 100Mbps Full Duplex mode. The software
can read bit[15:12] to see which mode is selected after Auto-negotiation. This
bit is invalid when it is not in the Auto-negotiation mode.
100M Half Duplex Operation Mode:
After Auto-negotiation is completed, results will be written to this bit. If this bit is
1, it means the operation mode is a 100Mbps Half Duplex mode. The
software can read bit[15:12] to see which mode is selected after
Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode.
10M Full Duplex Operation Mode:
After Auto-negotiation is completed, results will be written to this bit. If this bit is
1, it means the operation mode is a 10Mbps Full Duplex mode. The software
can read bit[15:12] to see which mode is selected after Auto-negotiation. This
bit is invalid when it is not in the Auto-negotiation mode.
10M Half Duplex Operation Mode:
After Auto-negotiation is completed, results will be written to this bit. If this bit is
1, it means the operation mode is a 10Mbps Half Duplex mode. The software
can read bit[15:12] to see which mode is selected after Auto-negotiation. This
bit is invalid when it is not in the Auto-negotiation mode.
Reserved:
14
100HDX
1, RO
13
10FDX
1, RO
12
10HDX
1, RO
11:10
Reserved
00, RO
9
Reserved
1, RW
Reserved:
Write as 0, ignore on read
00001, RW PHY Address Bit 4:0
0000, RO Auto-negotiation Monitor Bits:
These bits are for debug only. The Auto-negotiation status will be written to
these bits.
8:4
3:0
PHYAD[4:0]
ANMB[3:0]
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