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參數(shù)資料
| 型號： | DM9102DE |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)NIC控制器 |
| 文件頁數(shù)： | 6/70頁 |
| 文件大?。?/td> | 2245K |
| 代理商： | DM9102DE |
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6
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
5. Pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power,
# = asserted Low
5.1 PCI Bus Interface Signals
Pin No.
128LQFP
113
INT#
Pin Name
I/O
Description
O/D
Interrupt Request
This signal will be asserted low when an interrupted condition
as defined in CR5 is set, and the corresponding mask bit in
CR7 is et.
System Reset
When this signal is low, the DM9102D performs the internal
system reset to its initial state.
PCI system clock
PCI bus clock that provides timing for DM9102D related to
PCI bus transactions.
Bus Grant
This signal is asserted low to indicate that DM9102D has
been granted ownership of the bus by the central arbiter.
Bus Request
The DM9102D will assert this signal low to request the
ownership of the bus.
Power Management Event.
The DM9102D drives it low to indicates that a power
management event has occurred.
Initialization Device Select
This signal is asserted high during the Configuration Space
read/write access.
Cycle Frame
This signal is driven low by the DM9102D master mode to
indicate the beginning and duration of a bus transaction.
Initiator Ready
This signal is driven low when the master is ready to
complete the current data phase of the transaction. A data
phase is completed on any clock when both IRDY# and
TRDY# are sampled asserted.
Target Ready
This signal is driven low when the target is ready to complete
the current data phase of the transaction. During a read, it
indicates that valid data is asserted. During a write, it
indicates that the target is prepared to accept data.
Device Select
The DM9102D asserts the signal low when it recognizes its
target address after FRAME# is asserted. As a bus master,
the DM9102D will sample this signal which insures its
destination address of the data transfer is recognized by a
target.
Stop
This signal is asserted low by the target device to request the
114
RST#
I
115
PCICLK
I
117
GNT#
I
118
REQ#
O
119
PME#
O/D
3
IDSEL
I
21
FRAME#
I/O
23
IRDY#
I/O
24
TRDY#
I/O
26
DEVSEL#
I/O
27
STOP#
I/O
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| DM9102 | Single Chip Fast Ethernet NIC controller |
| DM9102A | Single Chip Fast Ethernet NIC controller |
| DM9102AF | Single Chip Fast Ethernet NIC controller |
| DM9102AT | Single Chip Fast Ethernet NIC controller |
| DM9108APPLICATIONENGINEERINGNOTESONE | DM9108 Application Engineering notes one |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102DEP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9102H | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102HEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9103 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface |
| DM9103EP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Three Port Ethernet Switch Controller with PCI Interface |
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