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參數(shù)資料
| 型號(hào)： | DM9338 |
| 文件頁數(shù)： | 14/43頁 |
| 文件大?。?/td> | 509K |
| 代理商： | DM9338 |
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DM9331
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
14
Preliminary
Version: DM9331-DS-P02
September 21, 2001
100Base-TX Receiver
The 100Base-TX receiver contains several function blocks
that convert the scrambled 125Mb/s serial data to
synchronous 2-bit nibble data that is then provided to the
MCI.
The receive section contains the following functional blocks:
- Signal Detect
- Digital Adaptive Equalizer
- MLT-3 to NRZI Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
Signal Detect
The signal detect function meets the specifications
mandated by the ANSI XT12 TP-PMD 100Base-TX
Standards for both voltage thresholds and timing
parameters.
Adaptive Equalizer
When transmitting data at high speeds over copper twisted
pair cable, attenuation based on frequency becomes a
concern. In high speed twisted pair signaling, the frequency
content of the transmitted signal can vary greatly during
normal operation based on the randomness of the
scrambled data stream. This variation in signal attenuation
caused by frequency variations must be compensated for to
ensure the integrity of the received data. In order to ensure
quality transmission when employing MLT-3 encoding, the
compensation must be able to adapt to various cable
lengths and cable types depending on the installed
environment. The selection of long cable lengths for a given
implementation, requires significant compensation which will
be over-kill in a situation that includes shorter, less
attenuating cable lengths. Conversely, the selection of short
or intermediate cable lengths requiring less compensation
will cause serious under-compensation for longer length
cables. Therefore, the compensation or equalization must
be adaptive to ensure proper conditioning of the received
signal independent of the cable length.
MLT-3 to NRZI Decoder
The DM9331 decodes the MLT-3 information from the
Digital Adaptive Equalizer into NRZI data.
Clock Recovery Module
The Clock Recovery Module accepts NRZI data from the
MLT-3 to NRZI decoder. The Clock Recovery Module locks
onto the data stream and extracts the 125MHz reference
clock. The extracted and synchronized clock and data are
presented to the NRZI to NRZ Decoder.
NRZI to NRZ
The transmit data stream is required to be NRZI encoded in
for compatibility with the TP-PMD standard for 100Base-TX
transmission over Category-5 unshielded twisted pair cable.
This conversion process must be reversed on the receive
end. The NRZI to NRZ decoder, receives the NRZI
data stream from the Clock Recovery Module and
converts it to a NRZ data stream to be presented to
the Serial to Parallel conversion block.
Serial to Parallel
The Serial to Parallel Converter receives a serial data
stream from the NRZI to NRZ converter, and converts
the data stream to parallel data to be presented to the
descrambler.
Descrambler
Because of the scrambling process required to control the
radiated emissions of transmit data streams, the receiver
must descramble the receive data streams. The
descrambler receives scrambled parallel data streams from
the Serial to Parallel converter, descrambles the data
streams, and presents the data streams to the Code Group
alignment block.
Code Group Alignment
The Code Group Alignment block receives un-aligned
5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after
the J/K is detected, and subsequent data is aligned on
a fixed boundary.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9338 WAF | 制造商:Texas Instruments 功能描述: |
| DM9338J/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Register File |
| DM9338N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Multiple Port Register |
| DM9338W/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DM933N | 制造商:Texas Instruments 功能描述: |
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