DM9331
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
2
Preliminary
Version: DM9331-DS-P02
September 21, 2001
Table of Contents
General Description..................................................1
Block Diagram ..........................................................1
Features....................................................................4
Pin Configuration: DM9331 LQFP ............................5
Pin Description..........................................................6
Media Converter Interface, 19 pins .......................6
Media Interface, 5 pins ..........................................7
LED Interface, 3 pins.............................................7
Mode, 1 pin............................................................8
Bias and Clock, 3 pins...........................................8
Power, 15 pins.......................................................8
Table A ..................................................................8
LED Configuration.....................................................9
Functional Description ............................................10
MCI interface .......................................................10
100Base-TX Operation........................................11
100Base-TX Transmit .........................................11
100Base-TX Operation........................................12
4B5B Encoder......................................................12
Scrambler............................................................12
Parallel to Serial Converter..................................12
NRZ to NRZI Encoder .........................................12
NRZI to MLT-3.....................................................12
MLT-3 Driver........................................................12
4B5B Code Group ...............................................13
100Base-TX Receiver .........................................14
Signal Detect .......................................................14
Adaptive Equalizer...............................................14
MLT-3 to NRZI Decoder......................................14
Clock Recovery Module.......................................14
NRZI to NRZ........................................................14
Serial to Parallel...................................................14
Descrambler........................................................14
Code Group Alignment........................................14
4B5B Decoder .....................................................15
Auto-Negotiation..................................................15
MII Serial Management .......................................16
Serial Management Interface ..............................16
Management Interface – Read Frame Structure.16
Management Interface – Write Frame Structure 16
Power Reduced Mode.........................................17
Power Down Mode..............................................17
Reduced Transmit Power Mode..........................17
Link Fault Propagation ........................................17
MII Register Description .........................................18
- Key to Default.......................................................18
Basic Mode Control Register (BMCR) - 00.............19
Basic Mode Status Register (BMSR) - 01..............20
Auto-negotiation Advertisement Register (ANAR)
- 04..........................................................................21
Auto-negotiation Link Partner Ability Register
(ANLPAR) - 05........................................................21
Auto-negotiation Expansion Register (ANER)
- 06..........................................................................22
DAVICOM Specified Configuration Register (DSCR)
- 16..........................................................................23
DAVICOM Specified Configuration and Status
Register (DSCSR) - 17...........................................24
DAVICOM Specified Interrupt Register - 21...........25
Absolute Maximum Ratings....................................26
Operating Conditions...........................................26
Comments...........................................................26
DC Electrical Characteristics..................................27
AC Electrical Characteristics & Timing Waveforms
................................................................................28
TP Interface.........................................................28
Oscillator Timing..................................................28
MDC/MDIO Timing..............................................28
MDIO Timing when OUTPUT by STA.................29
MDIO Timing when OUTPUT by DM9331...........29
Auto-negotiation and Fast Link Pulse Timing
Parameters..........................................................29
Auto-negotiation and Fast Link Pulse Timing
Diagram...............................................................29
TXD to TP or FX Transmit Latency Timing Diagram
............................................................................30
TXD to TP or FX Transmit Latency Parameters.30
TP or FX to RXD Receive Latency Timing Diagram
............................................................................30
TP or FX to RXD Receive Latency Parameters..30
Application Notes....................................................31