DRAM
Controller
Maximum Clock
Frequency
Package
Type
Bus Width
Supporting
Largest DRAM
Possible
DP8440V-40
40 MHz
84-Pin PLCC
8, 16, 32
16 Mbits
DP8440VLJ-40
40 MHz
100-Pin PQFP
8, 16, 32
16 Mbits
DP8440VLJ-25
25 MHz
100-Pin PQFP
8, 16, 32
16 Mbits
DP8441VLJ-40
40 MHz
100-Pin PQFP
8, 16, 32, 64
64 Mbits
DP8441VLJ-25
25 MHz
100-Pin PQFP
8, 16, 32, 64
64 Mbits
Table of Contents
1.0 CONNECTION DIAGRAMS
2.0 FUNCTIONAL INTRODUCTION
3.0 SIGNAL DESCRIPTION
3.1 Address and Control Signals
3.2 DRAM Control Signals
3.3 Refresh Signals
3.4 Reset and Programming Signals
3.5 Clock Inputs
3.6 Power Signals and Capacitor Input
4.0 PROGRAMMING AND RESETTING
4.1 Reset
4.2 Programming Sequence
4.3 Programming Selection Bits
5.0 ACCESS MODES
5.1 Opening Access
5.2 Normal Mode
5.3 Page Mode
5.4 Burst Access
5.5 Inner Page Burst Access
6.0 REFRESH MODES
6.1 Auto-Internal Refresh
6.2 Externally Controlled Refresh
6.3 Error Scrubbing during Refresh
6.4 Extending Refresh
6.5 Refresh Types
7.0 WAIT SUPPORT
7.1 DTACK During Opening Access
7.2 DTACK During Page Access
7.3 DTACK During Burst Access
7.4 Next Address or Early DTACK Support
8.0 ABSOLUTE MAXIMUM RATINGS
9.0 DC ELECTRICAL CHARACTERISTICS
10.0 LOAD CAPACITANCE
11.0 AC TIMING PARAMETERS
12.0 AC TIMING WAVEFORMS
CLK and DECLK Timing
Refresh Timing
Refresh and Access Timing
Programming and Initialization Period Timing
Normal Mode Access Timing
Page Mode Access Timing
Burst Mode Access Timing
13.0 ERRATA
14.0 PHYSICAL DIMENSIONS
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