參數(shù)資料
型號(hào)： DP8440V
英文描述： DRAM Controller
中文描述： DRAM控制器
文件頁(yè)數(shù)： 27/46頁(yè)
文件大?。?/td> 644K
代理商： DP8440V
7.0 Wait Support
(Continued)
7.3 BURST ACCESSES
During burst accesses, DTACK will assert from the clock
edge chosen through programming bit ECAS2. CAS auto-
matically negates and the controller guarantees the mini-
mum CAS precharge time according to programming bit C9.
CAS and DTACK can be programmed to assert from either
clock edge.
During burst accesses, the input BSTARQ must be asserted
for CAS to toggle. Figure 23 shows how DTACK asserts
during burst accesses, following an opening access with
one wait state. In Figure 23a, when the number of wait
states in a burst is programmed to zero, DTACK remains
asserted throughout the burst. The address is not incre-
mented by the DRAM controller. It is the responsibility of the
user to provide incrementing addresses.
For the controller to increment the column address DTACK
must toggle.
TL/F/11718–20
FIGURE 23a. 1T during Opening and 0T during Burst. DTACK stays asserted during the burst.
TL/F/11718–21
FIGURE 23b. 1T during Opening, 1T during Burst
TL/F/11718–22
FIGURE 23c. 1T during Opening, 2T during Burst
TL/F/11718–23
FIGURE 23d. 1T during Opening, 3T during Burst
27
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