參數(shù)資料
型號： DP8441
文件頁數(shù)： 32/46頁
文件大?。?/td> 644K
代理商： DP8441
11.0 AC Timing Parameters
(Continued)
Y
Symbol
Description
DP8440/41-40
40 MHz Devices
DP8440/41-25
25 MHz Devices
Min
Max
Min
Max
FAST ACCESS PARAMETER
400
t
PCKCASL
CLK High to CAS Asserted
15.5
16
401
t
PCKCASH
CLK High to CAS Negated
17.5
18
402
t
PCKLCASL
CLK Low to CAS Asserted
18.5
19
403
t
PCKLCASH
CLK Low to CAS Negated
18.5
19
404
t
WCASPC
CAS Precharge when Programmed as
(/2
T during Burst
10
10
405
t
PCKCASB
CLK to CAS Asserted when Programmed as
(/2
T during Burst
17
35
17
36
406
t
PCKCVB
CLK to Column Address Valid when B0
e
1 during Programming
27
27
407
t
PCKCVLB
CLK to Column Address Valid when B0
e
0 during Programming
32
32
408
t
PCKPMH
CLK to PAGMISS Asserted During Burst and NoWRAP
14
14
409
t
SBARCK
BSTARQ Asserted Setup to CLK
10
10
410
t
HBARNCK
BSTARQ Asserted Hold from CLK (CLK following DTACK Negation)
16
17
411
t
SNWCK
NoWRAP Asserted Setup to CLK (NADTACK)
5
6
412
t
HNWCK
NoWRAP Asserted Hold from CLK (DTACK)
5
6
413
t
SNLADS
NoLATCH Asserted Setup to ADS
5
6
414
t
HNLCK
NoLATCH Asserted Hold from CLK
5
6
415
t
SPMCK
PAGMISS Input Asserted Setup to CLK
16
16
416
t
HPMCK
PAGMISS Input Asserted Hold from CLK
5
6
417
t
PADDPMH
Row and Bank Address Valid to PAGMISS Asserted
13
13
418
t
PCKPML
CLK High to PAGMISS Negated
17
17
419
t
SWICLK
WAITIN Asserted Setup to CLK (NADTACK)
5
6
420
t
HWICLK
WAITIN Asserted Hold from CLK (NADTACK)
5
6
421
t
SADSCKP
ADS Setup to CLK in Page Mode
22
22
422
t
PADSPMH
ADS to PAGMISS High in Page Mode
16
16
423
t
HADSCKP
ADS Hold from CLK before Assertion in Page Mode
4
4
424
t
SCSKP
CS Setup to CLK in Page Mode
22
22
12.0 AC Timing Waveforms: DP8440/41
TL/F/11718–27
FIGURE 25. CLK and DELCLK Timing
Number
DP8440/41-40
DP8440/41-25
Min
Max
Min
Max
1
25
40
2
10
15
3
10
15
4
25
25
5
10
10
6
10
10
32
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