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參數(shù)資料

5.0 Accessing Modes

(Continued)

5.3 PAGE MODE ACCESS

When the DP8440/41 is programmed for Page Accesses,

every access after the opening access needs a new ad-

dress and a new ADS. During Page Mode the DRAM con-

troller keeps RAS asserted until there is a page miss detect-

ed. When a new access is requested,

CAS asserts from

the rising CLK edge that ADS is set up to for reads, and

is delayed 1 clock for writes.

DTACK asserts according to

the programming selection in bits R6–7. At the end of a

page access only CAS and DTACK negate and they negate

on the same clock edge.

During page accesses only CAS and DTACK toggle until

there is a page miss. When a page miss is detected, the

DP8440/41 will negate RAS and meet the programmed pre-

charge time. CPUs with page comparators can program the

DRAM controller’s page comparator as an input. When this

input asserts, it indicates that a page change has occurred,

RAS will negate and the controller will meet the precharge

time. Figure 8 shows an opening access followed by two

page accesses. The first page access is a ‘‘page hit,’’ the

second access is out of page.

TL/F/11718–7

FIGURE 8. Opening Access Followed by Page Accesses

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
DP84422J	制造商:未知廠家制造商全稱:未知廠家功能描述:DRAM Controller
DP84422J/A+	制造商:未知廠家制造商全稱:未知廠家功能描述:DRAM Controller
DP84422N	制造商:未知廠家制造商全稱:未知廠家功能描述:DRAM Controller
DP84422N/A+	制造商:未知廠家制造商全稱:未知廠家功能描述:DRAM Controller
DP84422N/B+	制造商:未知廠家制造商全稱:未知廠家功能描述:DRAM Controller

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