參數資料
型號: DP84422N
英文描述: DRAM Controller
中文描述: DRAM控制器
文件頁數: 24/46頁
文件大?。?/td> 644K
代理商: DP84422N
6.0 Refresh Modes
(Continued)
6.5 REFRESH TYPES
The DP8440/41 support RAS Only refresh and CAS-before-
RAS refresh. RAS only refresh can be programmed to be
staggered or non-staggered. Staggered refresh reduces
peak current requirements and system noise.
The DP8440/41 have a large enough refresh address coun-
ter for error scrubbing during refresh. If error scrubbing is
desired, the user must select the All RAS refresh option.
TL/F/11718–12
FIGURE 18. All RAS Refresh with 2Ts of RAS Low and Precharge.
All RAS refresh must be programmed when doing Error Scrubbing.
TL/F/11718–13
FIGURE 19. Staggered Refresh with 2Ts RAS low and Precharge.
Staggered refresh is good for noise sensitive systems.
Clearing the Refresh Counter and Refresh Clock:
The
user can clear the refresh counter by pulsing RFSH low for
two clocks while DISRFSH is negated. If RFSH is kept as-
serted for 500 ns, the refresh clock will also be cleared.
TL/F/11718–34
24
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相關代理商/技術參數
參數描述
DP84422N/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
DP84422N/B+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
DP84432J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
DP84432J/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller
DP84432N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller