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參數(shù)資料
| 型號： | DP84422N |
| 英文描述： | DRAM Controller |
| 中文描述： | DRAM控制器 |
| 文件頁數(shù)： | 9/46頁 |
| 文件大小： | 644K |
| 代理商： | DP84422N |
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3.0 Signal Descriptions
(Continued)
3.5 CLOCK INPUTS
Pin
Name
Device (if not
Applicable to All)
Input/
Output
Description
CLK
I
SYSTEM CLOCK:
This input may be in the range of 500 kHz to 40 MHz. This input is
generally a constant frequency but it may be controlled externally to change frequencies
for some arbitrary reason. This input provides the clock to the internal state machine that
arbitrates between accesses and refreshes. This clock’s positive edges and negative
edges are used to extend the DTACK signal. This clock is also used as a reference for the
RAS precharge time, the RAS low during refresh time and CAS precharge time.
DELCLK
I
DELAY LINE CLOCK:
The clock input DELCLK, may be in the range of 10 MHz to 40 MHz
and should be a multiple of 2 to have the DP8440/41 switching characteristics hold. If
DELCLK is not one of the above frequencies, the accuracy of the internal delay line will
suffer. This happens because the phase lock loop that generates the delay line assumes
an input clock frequency multiple of 2 MHz.
For example, if DELCLK input is 17 MHz and we choose to divide by 8 (program bits
C0–3), this will produce 2.125 MHz which is 6.25% off of 2 MHz. Therefore, the
DP8440/41 delay line will produce delays that are shorter (faster delays) than intended. If
divide by 9 was chosen, the delay line would produce longer delays (slower delays) than
intended (1.89 MHz instead of 2 MHz). This clock is also divided to create the internal
refresh clock.
3.6 POWER SIGNALS AND CAPACITOR INPUT
Pin
Name
Device (if not
Applicable to All)
Input/
Output
Description
V
CC
I
POWER:
Supply Voltage.
GND
I
GROUND:
Supply Voltage Reference.
CAP
I
CAPACITOR:
This input is used by the internal PLL for stabilization. The value of the
ceramic capacitor should be 0.1
m
F and it should be connected between this input and
ground.
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DP84432J | DRAM Controller |
| DP84432N | DRAM Controller |
| DP8472 | Floppy Disk Controller |
| DP8472J | Floppy Disk Controller |
| DP8472N | Floppy Disk Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DP84422N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84422N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84432J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84432J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84432N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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