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參數(shù)資料
| 型號(hào)： | DPL4519 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Sound Processor for Digital and Analog Surround Systems |
| 中文描述： | 聲音處理器的數(shù)字和模擬環(huán)繞聲系統(tǒng) |
| 文件頁數(shù)： | 56/64頁 |
| 文件大?。?/td> | 1073K |
| 代理商： | DPL4519 |
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DPL 4519G
PRELIMINARY DATA SHEET
56
Micronas
Fig. 4–22:
I
2
S timing diagram (asynchronous interface)
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Analog Ground
V
AGNDC0
AGNDC Open Circuit Voltage
AHVSUP = 8 V
AHVSUP = 5 V
AGNDC
3.8
2.5
V
V
R
load
≥
10 M
R
outAGN
AGNDC Output Resistance
AHVSUP = 8 V
AHVSUP = 5 V
70
47
125
83
180
120
k
k
3 V
≤
V
AGNDC
≤
4 V
Analog Input Resistance
R
inSC
SCART Input Resistance
from T
A
= 0 to 70
°
C
SCn_IN_s
1)
25
40
58
k
f
signal
= 1 kHz, I = 0.05 mA
R
inMONO
MONO Input Resistance
from T
A
= 0 to 70
°
C
MONO_IN
15
24
35
k
f
signal
= 1 kHz, I = 0.1 mA
1)
“n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”
Right aligned (I
2
S_CONFIG[11] = 1, I
2
S_CONFIG[9] = 0)
16 Bit data & 16...32 clocks allowed
I2S_WS3
I2S_CL3
I2S_DA_IN3
MSB
1/F
I2S3WS
1/F
I2S3CL
I2S_CL3
I2S_DA_IN3
I2S_WS3
T
h_I2S3
Right sample (I
2
S_CONFIG[10] = 0)
Right sample (I
2
S_CONFIG[10] = 1)
Left sample (I
2
S_CONFIG[10] = 0)
Left sample (I
2
S_CONFIG[10] = 1)
MSB
LSB
MSB
MSB
LSB
I2S_DA_IN3
I2S_DA_IN3
Left aligned (I
2
S_CONFIG[9] = 0)
16,18...32 Bit data & clocks allowed
Left aligned (I
2
S_CONFIG[9] = 1)
16,18...32 Bit data & clocks allowed
T
s_I2S3
T
s_I2S3
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