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參數(shù)資料
| 型號： | DS1338Z-3+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC 56BYTE NV RAM 3V 8-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/日歷 |
| 特點： | 閏年，NVSRAM，方波輸出 |
| 存儲容量： | 56B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
DS1338 I2C RTC with 56-Byte NV RAM
4 of 16
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 1, Figure 1)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Recovery at Power-Up (Note 15)
tREC
2
ms
VCC Fall Time; VPF(MAX) to VPF(MIN)
tVCCF
300
s
VCC Rise Time; VPF(MIN) to VPF(MAX)
tVCCR
0
s
Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause
loss of data.
Note 1:
Limits at -40°C are guaranteed by design and not production tested.
Note 2:
All voltages are referenced to ground.
Note 3:
SCL only.
Note 4:
SDA and SQW/OUT.
Note 5:
ICCA—SCL clocking at max frequency = 400kHz.
Note 6:
Specified with the I2C bus inactive.
Note 7:
Measured with a 32.768kHz crystal attached to X1 and X2.
Note 8:
After this period, the first clock pulse is generated.
Note 9:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 10:
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 11:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line
is released.
Note 12:
CB—total capacitance of one bus line in pF.
Note 13:
Guaranteed by design. Not production tested.
Note 14:
The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V ≤ VCC ≤ VCC(MAX) and 1.3V ≤ VBAT ≤ 3.7V.
Note 15:
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.
Figure 1. Power-Up/Power-Down Timing
OUTPUTS
VCC
VPF(MAX)
VPF(MIN)
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZED
VALID
tVCCF
tVCCR
tREC
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