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參數(shù)資料
| 型號(hào)： | DS1338Z-3+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 0K |
| 描述： | IC RTC 56BYTE NV RAM 3V 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 閏年，NVSRAM，方波輸出 |
| 存儲(chǔ)容量： | 56B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
DS1338 I2C RTC with 56-Byte NV RAM
8 of 16
OPERATION
The DS1338 operates as a slave device on the serial bus. Access is obtained by implementing a START condition
and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially
until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is
greater than VPF. However, when VCC falls below V
PF, the internal clock registers are blocked from any access. If
VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is greater
than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The oscillator and
timekeeping functions are maintained from the VBAT source until VCC is returned to nominal levels. The block
diagram (Figure 3) shows the main elements of the DS1338.
An enable bit in the seconds register controls the oscillator. Oscillator startup times are highly dependent upon
crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major
contributors to long start-up times. A circuit using a crystal with the recommended characteristics and proper layout
usually starts within 1 second.
POWER CONTROL
The power-control function is provided by a precise, temperature-compensated voltage reference and a
comparator circuit that monitors the VCC level. The device is fully accessible and data can be written and read when
VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any
access. If VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is
greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The registers are
maintained from the VBAT source until VCC is returned to nominal levels (Table 1). After VCC returns above VPF, read
and write access is allowed after tREC (Figure 1). On the first application of power to the device the time and date
registers are reset to 01/01/00 01 00:00:00 (DD/MM/YY DOW HH:MM:SS). The CH bit in the seconds register will be set
to a 0.
Table 1. Power Control
SUPPLY
CONDITION
READ/WRITE
ACCESS
POWERED
BY
VCC < VPF, VCC < VBAT
No
VBAT
VCC < VPF, VCC > VBAT
No
VCC
VCC > VPF, VCC < VBAT
Yes
VCC
VCC > VPF, VCC > VBAT
Yes
VCC
OSCILLATOR CIRCUIT
The DS1338 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or
capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a
functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal
with the specified characteristics.
Table 2. Crystal Specifications*
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Nominal Frequency
fO
32.768
kHz
Series Resistance
ESR
50
k
Load Capacitance
CL
12.5
pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to
Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
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