DS1338 I2C RTC with 56-Byte NV RAM 11 of 16 CONTROL REGISTER (07H) The control r" />
參數(shù)資料
型號: DS1338Z-3+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC RTC 56BYTE NV RAM 3V 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 時鐘/日歷
特點: 閏年,NVSRAM,方波輸出
存儲容量: 56B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.3 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
DS1338 I2C RTC with 56-Byte NV RAM
11 of 16
CONTROL REGISTER (07H)
The control register controls the operation of the SQW/OUT pin and provides oscillator status.
Bit #
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Name
OUT
0
OSF
SQWE
0
RS1
RS0
POR
1
0
1
0
1
Bit 7: Output Control (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is
disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0.
Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for
some time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered,
and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a
STOP condition. The following are examples of conditions that may cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC and VBAT are insufficient to support oscillation.
3) The CH bit is set to 1, disabling the oscillator.
4) External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to
logic 1 leaves the value unchanged.
Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with
either VCC or VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1
bits.
Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output when the
square-wave output has been enabled. The table below lists the square-wave frequencies that can be selected
with the RS bits.
Square-Wave Output
OUT
RS1
RS0
SQW OUTPUT
SQWE
X
0
1Hz
1
X
0
1
4.096kHz
1
X
1
0
8.192kHz
1
X
1
32.768kHz
1
0
X
0
1
X
1
0
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